来自这里的代码: http: //esd.cs.ucr.edu/labs/tutorial/latch.vhd
--------------------------------------------
-- Simple D Latch (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- latch is simply controlled by enable bit
-- but has nothing to do with clock signal
-- notice this difference from flip-flops
--------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
entity D_latch is
port( data_in: in std_logic;
enable: in std_logic;
data_out: out std_logic
);
end D_latch;
architecture behv of D_latch is
begin
-- compare this to D flipflop
process(data_in, enable)
begin
if (enable='1') then
-- no clock signal here
data_out <= data_in;
end if;
end process;
end behv;
为什么“data_in”需要在敏感列表中?我知道流程需要它来分配,但是流程功能基于启用输入。
谢谢