1

来自这里的代码: http: //esd.cs.ucr.edu/labs/tutorial/latch.vhd

--------------------------------------------
-- Simple D Latch (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- latch is simply controlled by enable bit
-- but has nothing to do with clock signal
-- notice this difference from flip-flops
--------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;

entity D_latch is
port(   data_in:    in std_logic;
    enable:     in std_logic;
    data_out:   out std_logic
);
end D_latch;

architecture behv of D_latch is
begin       

    -- compare this to D flipflop

    process(data_in, enable)
    begin
        if (enable='1') then
            -- no clock signal here
        data_out <= data_in;  
    end if;
    end process;    

end behv;

为什么“data_in”需要在敏感列表中?我知道流程需要它来分配,但是流程功能基于启用输入。

谢谢

4

1 回答 1

0

对于 D 锁存器,只要启用为“1”,您就需要 data_out=data_in。因此,如果 data_in 更改而 enable 保持为“1”,则 data_out 必须更改。如果 data_in where 不在敏感列表中,则不会发生这种情况。

于 2014-02-13T19:44:03.707 回答