我是一名模拟工程师,试图为我的项目学习 VHDL。该项目是计算输入信号的上升沿并将计数预分频为较小的数字。例如,如果输入有 8 个计数,则将输出 1 个计数。预分频值可以由用户更改。我已经设法完成了预分频部分,但在当前输出将不断变高。
我想要做的是,一旦预分频计数 = 用户选择的值,然后输出 500 ns 脉冲而不是恒定逻辑高电平。
我有一个 50 MHz 的时钟,所以输出需要在 25 个锁定周期内保持高电平,但是我不确定如何做到这一点。
任何帮助都会很棒:)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (
pushbutton: in std_logic;
SW: in std_logic_vector(7 downto 0); -- user select switches
RESET: in std_logic;
OUTPUT: out std_logic;
LEDS: out std_logic_vector(8 downto 0) -- un used leds
);
end counter;
architecture Behavioral of counter is
signal COUNTER: std_logic;
signal PRESCALER: std_logic_vector(7 downto 0);
signal SWITCH: std_logic_vector(7 downto 0);
begin
CounterProcess: process(RESET, pushbutton)
begin
if rising_edge(pushbutton) then
if RESET = '0' then
PRESCALER <= (others => '0');
COUNTER <= '0';
else
if PRESCALER < SWITCH - 1 then
PRESCALER <= PRESCALER + 1;
else
PRESCALER <= (others => '0');
COUNTER <= '1';
end if;
end if;
end if;
end process;
LEDS <= (others => '0'); -- Turn off all unsed LEDs
SWITCH <= SW; -- Asign switch value into a signal
OUTPUT <= COUNTER;
end Behavioral;