我正在为我的设计编写一个通用测试台,它通过一条非常标准的总线与 RAM 通信。我查阅了一些例子并这样写:
signal memory: mem_array;
signal mem_address: std_logic_vector(31 downto 0);
signal mem_data: std_logic_vector(31 downto 0);
signal mem_read: std_logic;
signal mem_write: std_logic;
cpu_mem_data <= transport memory(to_integer(unsigned(mem_address))) after DELAY when mem_read = '1' else (others => 'Z');
always : PROCESS
file in_file: text open read_mode is "in.txt";
variable line_str: line;
variable address: std_logic_vector(31 downto 0);
variable data: std_logic_vector(31 downto 0);
BEGIN
reset <= '1';
readline(in_file, line_str);
hread(line_str, address);
starting_pc <= address;
while not endfile(in_file) loop
readline(in_file, line_str);
hread(line_str, address);
read(line_str, data);
memory(to_integer(unsigned(address))) <= data;
report "Initialized " & integer'image(to_integer(unsigned(address))) & " to " & integer'image(to_integer(unsigned(data)));
end loop;
wait for 30 ns;
reset <= '0';
WAIT;
END PROCESS always;
process (mem_write)
begin
if (rising_edge(mem_write)) then
memory(to_integer(unsigned(mem_address))) <= transport mem_data after DELAY;
report "Will write " & integer'image(to_integer(unsigned(mem_data))) & " to " & integer'image(to_integer(unsigned(mem_address)));
end if;
end process;
我遇到了两个问题。
在 ModelSim Altera SE 中编译和仿真时,内存显示所有位置的所有 X。报告显示从 in.txt 文件中读取了正确的值,但没有写入内存。我还尝试将所有位置或仅将单个位置初始化为全“0”,但它也不起作用。相反,信号starting_pc 被设置为正确值。
另一个问题是延迟分配似乎不起作用。我的设计尝试从内存中读取,并且 mem_read 和 mem_address 设置正确,但在 DELAY 时间之后 mem_data 保持高阻抗。
我究竟做错了什么?