我尝试实现一个具有异步预设和清除的 JK 触发器,时钟上具有正沿逻辑。
我从 Altera Quartus II 收到以下错误:
错误 (10822):JK_FF_PE_D1.vhd(52) 处的 HDL 错误:无法在此时钟沿实现分配寄存器
错误:无法详细说明顶级用户层次结构
我没有看到错误...我将非常感谢您的提示或建议。
先感谢您!
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF_PE_D1 is
port(
J, K : in std_logic; -- J, K inputs of flip flop
PS : in std_logic; -- Preset of flip flop
CLR : in std_logic; -- CLR of flip flop
CLK : in std_logic; -- Clock
Q, Qcompl : out std_logic -- Q and its complementary output
);
end entity JK_FF_PE_D1;
architecture simple of JK_FF_PE_D1 is
signal temp_Q, temp_Qcompl : std_logic;
begin
p0:process(PS, CLR, CLK) is
begin
case std_logic_vector'(PS, CLR) is
when "00" =>
temp_Q <= '1';
temp_Qcompl <= '1';
when "01" =>
temp_Q <= '1';
temp_Qcompl <= '0';
when "10" =>
temp_Q <= '0';
temp_Qcompl <= '1';
when others => -- Preset = 1 , Clear = 1
if rising_edge (CLK) then -- Clock turns from 0 -> 1
case std_logic_vector'(J, K) is
when "11" =>
temp_Q <= not temp_Q;
temp_Qcompl <= not temp_Qcompl;
when "10" =>
temp_Q <= '1';
temp_Qcompl <= '0';
when "01" =>
temp_Q <= '0';
temp_Qcompl <= '1';
when others =>
null;
end case;
end if;
end case;
end process p0;
Q <= temp_Q;
Qcompl <= not temp_Qcompl;
end architecture simple;