verilog - Verilog 代码编译没有错误但没有输出

Question

module encoder (op, in, clock, reset);
     
     //$display("We are in initial procedural block");

     input [15:0] in;
     input clock, reset;
     output [3:0] op;

     wire [15:0] in;
     wire clock, reset;

     reg [3:0] op;

     always @ ( posedge clock)
     begin
          $display("We are in initial procedural block");

          if (reset)
          begin
               $display("we are in the reset condition");
               op = 0;
          end
          else 
          begin
               case(in)
                    16'h0002: #1 op = 4'b0001;
                    16'h0004: #1 op = 4'b0010; 
                    16'h0008: #1 op = 4'b0011;
                    16'h0010: #1 op = 4'b0100;
                    16'h0012: #1 op = 4'b0101;
                    16'h0014: #1 op = 4'b0110; 
                    16'h0018: #1 op = 4'b0111;
                    16'h0020: #1 op = 4'b1000; 
                    16'h0022: #1 op = 4'b1001;
                    16'h0024: #1 op = 4'b1010; 
                    16'h0028: #1 op = 4'b1011;
                    16'h0030: #1 op = 4'b1100;
                    16'h0032: #1 op = 4'b1101;
                    16'h0034: #1 op = 4'b1110; 
                    16'h0038: #1 op = 4'b1111;
                    16'h0040: #1 op = 4'b0000;
                    default : $display("DEFAULT!!!");
               endcase 
          end
     end
endmodule

module encoder_tb;

     input in, reset, clock;
     output op;

     reg [15:0] in = 16'h0000;
     reg reset, clock;
     wire [3:0] op;

     //internal variable
     reg [15:0] incremental_value = 16'h0002;

     initial
     begin
          $monitor("time = %g,\tclock = %d,\tin = %h,\top = %b", 
                          $time,      reset,       in,       op );

          $display("We are in initial procedural block");

          in    = 0;
          reset = 0;
          clock = 0;
          op    = 0;
      #1  clock = !clock; 
      #10 reset = !reset;
      #5  in    = in + incremental_value; 
          #100 $finish;
     end

     always 
     begin
     #1  clock = !clock; 
     #10 reset = !reset;
     #5  in    = in + incremental_value; 
     end 

     encoder_tb test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );

     // Waveform Generation
     initial
     begin
          $dumpfile("encoder.vcd");
          $dumpvars(0,op,in,clock,reset);
     end
   
endmodule 

我试图创建一个 16 位输入到 4 位输出编码器。我能够编译我的代码而没有任何错误，但是在 [ iverilog encoder_tb.v -o encoder] & [ vvp encoder vcd] 命令之后，即使我已经给出$monitor了$display任何我能想到的语句，它也没有给我任何东西。我无法调试这个。

Answer 1

我在 2 个不同的模拟器（VCS 和 Incisive）上使用您的代码编译错误。也许您的模拟器编译了代码，但由于编码不佳而无法正确模拟。

该encoder_tb模块有inputandoutput语句，但没有端口列表。

该encoder_tb模块有一个自身的递归实例。

wire您对( )进行程序分配op。

当我进行这些更改时，我会得到一些输出：

module encoder (op, in, clock, reset);
     
     //$display("We are in initial procedural block");

     input [15:0] in;
     input clock, reset;
     output [3:0] op;

     wire [15:0] in;
     wire clock, reset;

     reg [3:0] op;

     always @ ( posedge clock)
     begin
          $display("We are in initial procedural block");

          if (reset)
          begin
               $display("we are in the reset condition");
               op = 0;
          end
          else 
          begin
               case(in)
                    16'h0002: #1 op = 4'b0001;
                    16'h0004: #1 op = 4'b0010; 
                    16'h0008: #1 op = 4'b0011;
                    16'h0010: #1 op = 4'b0100;
                    16'h0012: #1 op = 4'b0101;
                    16'h0014: #1 op = 4'b0110; 
                    16'h0018: #1 op = 4'b0111;
                    16'h0020: #1 op = 4'b1000; 
                    16'h0022: #1 op = 4'b1001;
                    16'h0024: #1 op = 4'b1010; 
                    16'h0028: #1 op = 4'b1011;
                    16'h0030: #1 op = 4'b1100;
                    16'h0032: #1 op = 4'b1101;
                    16'h0034: #1 op = 4'b1110; 
                    16'h0038: #1 op = 4'b1111;
                    16'h0040: #1 op = 4'b0000;
                    default : $display("DEFAULT!!!");
               endcase 
          end
     end
endmodule

module encoder_tb;

//     input in, reset, clock;
//     output op;

     reg [15:0] in = 16'h0000;
     reg reset, clock;
     wire [3:0] op;

     //internal variable
     reg [15:0] incremental_value = 16'h0002;

     initial
     begin
          $monitor("time = %g,\tclock = %d,\tin = %h,\top = %b", 
                          $time,      reset,       in,       op );

          $display("We are in initial procedural block");

          in    = 0;
          reset = 0;
          clock = 0;
//          op    = 0;
      #1  clock = !clock; 
      #10 reset = !reset;
      #5  in    = in + incremental_value; 
          #100 $finish;
     end

     always 
     begin
     #1  clock = !clock; 
     #10 reset = !reset;
     #5  in    = in + incremental_value; 
     end 

//     encoder_tb test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );
     encoder test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );

     // Waveform Generation
     initial
     begin
          $dumpfile("encoder.vcd");
          $dumpvars(0,op,in,clock,reset);
     end
   
endmodule 

输出：

We are in initial procedural block
time = 0,       clock = 0,      in = 0000,      op = xxxx
We are in initial procedural block
DEFAULT!!!
time = 16,      clock = 0,      in = 0004,      op = xxxx
We are in initial procedural block
time = 18,      clock = 0,      in = 0004,      op = 0010
time = 27,      clock = 1,      in = 0004,      op = 0010
time = 32,      clock = 1,      in = 0006,      op = 0010
time = 43,      clock = 0,      in = 0006,      op = 0010
time = 48,      clock = 0,      in = 0008,      op = 0010
We are in initial procedural block
time = 50,      clock = 0,      in = 0008,      op = 0011
time = 59,      clock = 1,      in = 0008,      op = 0011
time = 64,      clock = 1,      in = 000a,      op = 0011
time = 75,      clock = 0,      in = 000a,      op = 0011
time = 80,      clock = 0,      in = 000c,      op = 0011
We are in initial procedural block
DEFAULT!!!
time = 91,      clock = 1,      in = 000c,      op = 0011
time = 96,      clock = 1,      in = 000e,      op = 0011
time = 107,     clock = 0,      in = 000e,      op = 0011
time = 112,     clock = 0,      in = 0010,      op = 0011
We are in initial procedural block
time = 114,     clock = 0,      in = 0010,      op = 0100