我在使用 ModelSim Student Edition 10.2c 运行 Verilog 项目时遇到问题。一切都编译没有错误,但是我在运行时收到以下错误:
# vsim -gui work.testbench
# Loading work.testbench
# Loading work.circuit1_assign
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.2c/examples/circuit1_assign.v(14): Instantiation of 'OR' failed. The design unit was not found.
#
# Region: /testbench/c
# Searched libraries:
# C:/Modeltech_pe_edu_10.2c/examples/hw4
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.2c/examples/circuit1_assign.v(16): Instantiation of 'NOT' failed. The design unit was not found.
#
# Region: /testbench/c
# Searched libraries:
# C:/Modeltech_pe_edu_10.2c/examples/hw4
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.2c/examples/circuit1_assign.v(18): Instantiation of 'AND' failed. The design unit was not found.
#
# Region: /testbench/c
# Searched libraries:
# C:/Modeltech_pe_edu_10.2c/examples/hw4
# Loading work.t1
# Error loading design
由于我是 Verilog 的新手,我不知道这意味着什么。我认为这是我犯的一个简单错误,但我似乎无法解决它,也没有通过谷歌找到解决方案。有人知道我能做些什么才能使我的项目有效吗?
编辑:我相信这与无法包含文件 whereAND
和被定义有关。谷歌搜索后,我发现该文件必须放在项目目录中。但是,我已放置在正确的目录中,但它仍然无法正常工作。OR
NOT
modelsim.ini
modelsim.ini
编辑:我现在已经为我的项目发布了所有三个源文件(这只是测试组合电路......)这是我的电路1_assign.v代码:
module circuit1_assign
(
input x,
input y,
input z,
output f
);
wire w1, w2;
OR o1 (.i0(x), .i1(y), .o(w1));
NOT n1 (.i2(z), .o(w2));
AND a1 (.i3(w1), .i4(w2), .o(f));
endmodule
这是测试的代码:
`时间刻度 1ns/1ps
模块 t1(输出 reg a,输出 reg b,输出 reg c);
initial
begin
a = 0; //Do all combinations of possible input values
b = 0;
c = 0;
#10 a = 0;
#10 b = 0;
#10 c = 1;
#10 a = 0;
#10 b = 1;
#10 c = 0;
#10 a = 0;
#10 b = 1;
#10 c = 1;
#10 a = 1;
#10 b = 0;
#10 c = 0;
#10 a = 1;
#10 b = 0;
#10 c = 1;
#10 a = 1;
#10 b = 1;
#10 c = 0;
#10 a = 1;
#10 b = 1;
#10 c = 1;
#10 $finish;
end
endmodule
这是我的测试平台代码:
`timescale 1ns/1ps
module testbench();
wire l, m, n, o;
circuit1_assign c
(
.x (l),
.y (m),
.z (n),
.f (o)
);
t1 t
(
.a (l),
.b (m),
.c (n)
);
initial
begin
$monitor ($time,,"l=%b, m=%b, n=%b, o=%b",
l, m, n, o);
end
endmodule
提前致谢。