对于以下片段 Chisel 没有合成:
import Chisel._
import Node._
import scala.collection.mutable.HashMap
class PseudoLRU(val num_ways: Int) extends Module
{
val num_levels = log2Up(num_ways)
val io = new Bundle {
val last_used_cline = UInt(INPUT, width = num_levels)
val update_state = Bool(INPUT)
}
val state = Reg(Vec.fill(num_ways-1){Bool()})
private val msb = num_levels - 1
when (io.update_state) {
// process level 0
state(0) := !io.last_used_cline(msb, msb) // get the most significant bit
// process other levels
for (level <- 1 until num_levels) {
val offset = UInt((1 << level) - 1, width = log2Up(num_ways-1))
val bit_index = io.last_used_cline(msb, msb - level + 1) + offset
val pos = msb - level
val bit = io.last_used_cline(pos, pos)
state(bit_index) := !bit
}
}
}
object test_driver {
def main(args: Array[String]): Unit = {
val plru_inst = () => Module(new PseudoLRU(num_ways = 16))
chiselMain(args, plru_inst)
}
}
如果手动展开循环 for (level <- 1 until num_levels) 并折叠常量,则行为相同:
when (io.update_state) {
state( 0 ) := !io.last_used_cline(3, 3)
state( io.last_used_cline(3, 3) + UInt(1, width = 3) ) := !io.last_used_cline(2, 2)
state( io.last_used_cline(3, 2) + UInt(3, width = 3) ) := !io.last_used_cline(1, 1)
state( io.last_used_cline(3, 1) + UInt(7, width = 3) ) := !io.last_used_cline(0, 0)
}
为两个片段(原始和展开/实例化的 16 路案例)生成的 verilog(和类似的 C++ 代码):
module PseudoLRU(input reset,
input [3:0] io_last_used_cline,
input io_update_state
);
wire T0;
wire[151:0] T1;
assign T0 = ! reset;
endmodule
不太明白为什么只有虚拟结构 我应该怎么做才能强制综合逻辑?谢谢!