我的问题是我不知道实体加法器是对还是错。
我的另一个问题是我必须将实体加法器放在与实体 mult 相同的模块中?或者我应该创建另一个模块?
这是我的代码:是VHDL中两个5位数字的乘法代码。我不知道这是问题所在:库,信号或变量声明的站点,..?
`library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity mult is
port (op1 : in std_logic_vector(4 downto 0);--a
op2 : in std_logic_vector(4 downto 0);--x
out : out std_logic_vector(9 downto 0)); --pp
end mult;
architecture Behavioral of mult is
type t_matrix is array (0 to 5, 10 downto 0) of std_logic;
signal c, sum, mul : t_matrix ;
signal sum_ini : std_logic_vector(9 downto 0) ;
begin
rows : for i in 0 to 3 generate
columns : for j in 0 to 9 generate
i_u : adder port map(a => sum_ini(j),
b =>c(i,j),
cin => mul(i, j),
sum => sum(i+1, j),
cout => c(i+1, j+1));
end generate columns;
end generate rows;
p_multiplications : process (a, b)
--variable v_producto : t_pp := ((others => (others => ’0’)));
begin -- process multiplications
for i in 0 to 4 loop
for j in 0 to 4 loop
if i = 0 then
sum_ini(j) <= a(0) and b(j);
else
mul(i-1, j+i) <= a(i) and b(j);
end if;
end loop; -- j
end loop; -- i
end process p_multiplications;
end Behavioral;´
--I have another module my entity adder , but I don´t know where is the problem.
`entity adder is
port ( a : in std_logic_vector (9 downto 0));
end adder;
architecture Behavioral of adder is
type t_matrix is array (0 to 5, 10 downto 0) of std_logic;
signal cout, b, cin, sum : t_matrix ;
begin
sum <= (a xor cin) xor b;
cout <= (a and b)or(cin and a)or(cin and b);
end Behavioral;´