I am trying to create a carry-look-ahead adder/subtractor unit as part of an ALU using VHDL. unlike a conventional adder, this unit must recognize both 32-bit unpacked data and 16-bit packed data and treat them accordingly. So, if I choose to add two 32-bit unpacked quantities, it should give me a 32-bit unpacked result. However, if I want to add four 16-bit packed quantities, it should give me two 16-bit packed results.
ie.
32_bit_A + 32_bit_B = 32_bit_A+B
16_bit_A + 16_bit_B, 16_bit_C + 16_bit_D = 16_bit_A+B, 16_bit_C+D
I've tried to implement such a thing using a MODE bit which will determine whether or not I'm using packed or unpacked data, however, my VHDL compiler keeps telling me that it it is expecting the generate keyword, among other errors that I am rather confused about. I should note that this design compiles and works perfectly for unpacked data, that is, without the conditional statements and cla4 and cla5. I would appreciate some explanation as to what I'm doing wrong. Thanks
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity thirty_two_bit_cla is
port
(
A : in std_logic_vector(31 downto 0); -- 32-bit augend
B : in std_logic_vector(31 downto 0); -- 32-bit addend
SUM : out std_logic_vector(31 downto 0); -- 32-bit sum
CARRY_OUT : out std_logic; -- carry out
CARRY_IN : in std_logic; -- carry in
P_G : out std_logic; -- group propagate
G_G : out std_logic; -- group generate
MODE : in std_logic -- 16 or 32-bit addition (0 or 1 respectively)
);
end thirty_two_bit_cla;
architecture structural of thirty_two_bit_cla is
signal G : std_logic_vector(1 downto 0); --generate signals
signal P : std_logic_vector(1 downto 0); --propagate signals
signal C : std_logic_vector(2 downto 0); --carry signals
begin
--Treat data as 32-bit unpacked
if(MODE = '1') then
sixteen_bit_cla0: entity sixteen_bit_cla port map(A=>A(15 downto 0),
B=>B(15 downto 0),
SUM=>SUM(15 downto 0),
CARRY_IN=>C(0),
P_G => P(0),
G_G => G(0));
sixteen_bit_cla1: entity sixteen_bit_cla port map(A=>A(31 downto 16),
B=>B(31 downto 16),
SUM=>SUM(31 downto 16),
CARRY_IN=>C(1),
P_G => P(1),
G_G => G(1));
C(0) <= CARRY_IN;
C(1) <= G(0) or (P(0) and C(0));
C(2) <= G(1) or (P(1) and C(1));
CARRY_OUT <= C(2);
G_G<=C(2);
P_G <= P(0) and P(1);
--Treat data as 16-bit packed
elsif (MODE = '0') then
sixteen_bit_cla4: entity sixteen_bit_cla port map(A=>A(15 downto 0),
B=>B(15 downto 0),
SUM=>SUM(15 downto 0),
CARRY_IN=>CARRY_IN);
sixteen_bit_cla5: entity sixteen_bit_cla port map(A=>A(31 downto 16),
B=>B(31 downto 16),
SUM=>SUM(31 downto 16),
CARRY_IN=>CARRY_IN);
end if;
end structural;
Errors:
# Compile Entity "thirty_two_bit_cla"
# Compile Architecture "structural" of Entity "thirty_two_bit_cla"
# Error: COMP96_0329: 32 bit cla.vhd : (26, 5): Generate statement must have a label.
# Error: COMP96_0019: 32 bit cla.vhd : (26, 20): Keyword 'generate' expected.
# Error: COMP96_0019: 32 bit cla.vhd : (52, 2): Keyword 'end' expected.
# Error: COMP96_0016: 32 bit cla.vhd : (52, 8): Design unit declaration expected.
# Compile Entity "sixteen_bit_cla"
# Error: COMP96_0019: 32 bit cla.vhd : (53, 43): Keyword 'is' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (53, 48): '(' expected.
# Error: COMP96_0028: 32 bit cla.vhd : (53, 48): Identifier or keyword expected.
# Error: COMP96_0015: 32 bit cla.vhd : (53, 48): ';' expected.
# Error: COMP96_0019: 32 bit cla.vhd : (53, 51): Keyword 'end' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (53, 51): ';' expected.
# Error: COMP96_0016: 32 bit cla.vhd : (53, 52): Design unit declaration expected.
# Compile Entity "sixteen_bit_cla"
# Error: COMP96_0019: 32 bit cla.vhd : (58, 45): Keyword 'is' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (58, 50): '(' expected.
# Error: COMP96_0028: 32 bit cla.vhd : (58, 50): Identifier or keyword expected.
# Error: COMP96_0015: 32 bit cla.vhd : (58, 50): ';' expected.
# Error: COMP96_0019: 32 bit cla.vhd : (58, 53): Keyword 'end' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (58, 53): ';' expected.
# Error: COMP96_0016: 32 bit cla.vhd : (58, 54): Design unit declaration expected.
# Compile failure 18 Errors 0 Warnings Analysis time : 16.0 [ms]
# ULM: Warning: ULM_0021 Architecture `structural' of entity `register_file.thirty_two_bit_cla' is not up-to-date.