vhdl - ALU + 移位寄存器

Question

我必须制作一个连接到移位寄存器的 8 位 ALU。我认为这是 ALU 的代码，但是将 8 位移位寄存器与复位和时钟连接起来的最佳方法是什么？我不确定如何使用内部信号来连接这两个组件，如果它们都有单独的

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;              -- Calling libary's to be used
use IEEE.NUMERIC_STD.ALL;

entity lu is
port(   Clk : in std_logic;                -- The clock signal
        A : in signed(7 downto 0);         -- The A Input
        B : in signed(7 downto 0);         -- The B Input
        OPCODE : in unsigned(2 downto 0);  -- Op code entered into ALU
        RES :in  std_logic;                -- The reset pin
        Q : out signed(7 downto 0)         -- The Output of LU
        );
end lu;                                    -- End Entity


architecture Behavioral of lu is

signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0'); --The signal declaration 

begin

Reg1 <= A;        -- Linking Reg1 Signal to Input A
Reg2 <= B;        -- Linking Reg2 Signal to Input B
Q <= Reg3;        -- Linking Output Q to Signal Reg3

process(Clk)

begin

    if(rising_edge(Clk)) then -- Calculate at the positive edge of clk
        case OPCODE is

            when "000" => 
                Reg3 <= Reg1 + Reg2;    -- Output is = to addition

            when "001" => 
                Reg3 <= Reg1 - Reg2;    -- Output is = to subtraction

            when "010" => 
                Reg3 <= not Reg1;       -- Output is = to NOT gate

            when "011" => 
                Reg3 <= Reg1 nand Reg2; -- Output is = to NAND gate 

            when "100" => 
                Reg3 <= Reg1 nor Reg2;  -- Output is = to NOR gate  

            when "101" => 
                Reg3 <= Reg1 and Reg2;  -- Output is = to AND gate

            when "110" => 
                Reg3 <= Reg1 or Reg2;   -- Output is = to OR gate 

            when "111" => 
                Reg3 <= Reg1 xor Reg2;  -- Output is = to XOR gate  


            when others =>              -- If anyother Input Outputs nothing
                NULL;

        end case;       
    end if;

end process;    

end Behavioral;

Answer 1

假设您的意思是向提供的 ALU 代码添加逻辑操作，您需要进行两处更改：

1）在端口列表中，增加opcode信号的宽度，以便您可以添加新的操作码值：

    OPCODE: in unsigned(3 downto 0); -- Operation selection for the ALU

2）在你的case语句中，只需添加新的条件和代码来执行逻辑操作：

    case OPCODE is
        ...

        when "1000" =>
            Reg3 <= Reg1 srl to_integer(Reg2);  -- Reg3 <= Reg1 shifted Reg2 bits to the right
        when "1001" =>
            Reg3 <= Reg1 sll to_integer(Reg2);  -- Reg3 <= Reg1 shifted Reg2 bits to the left
        when "1010" =>
            Reg3 <= Reg1 ror to_integer(Reg2);  -- Reg3 <= Reg1 rotated Reg2 bits to the right
        when "1011" =>
            Reg3 <= Reg1 rol to_integer(Reg2);  -- Reg3 <= Reg1 rotated Reg2 bits to the right
        when others =>
            Reg3 <= (others => '0');
    end case;