我是一个 vhdl 新手。我只使用 AND 和 OR 门为全加器编写了编码。我创建了一个测试平台来测试我的代码,并将其配置为刺激 A、B 和 Cin 的所有八种逻辑组合。当我运行模拟波形时,输入的波形是正确的,但输出的总和(在我的情况下是 H)只显示“U”。请有任何想法。
library ieee;
use ieee.std_logic_1164.all;
--This program describes behaviour of a full adder constructed using
-- AND and OR gates. It employs component method which describes behaviour of
--AND,OR and NOT gates and use them to build the final object
--Entity description of the full adder
entity full_add is
port (a,b,c:IN BIT; h:OUT BIT);
end entity full_add;
--Description the 3 input And Gate
entity And2 is
port (j,k,l:in BIT; m:out BIT);
end entity And2;
architecture ex1 of And2 is
begin
m <= (j AND k AND l);
end architecture ex1;
--Description of the four input OR gate
entity Or2 is
port (d,e,f,g:IN BIT; h:OUT BIT);
end entity Or2;
architecture ex1 of Or2 is
begin
h <= (d or e or f or g);
end architecture ex1;
--Description of the NOT gate
entity Not1 is
port(x:in BIT; y:out BIT);
end entity Not1;
architecture ex1 of Not1 is
begin
y <= not x;
end architecture ex1;
--Components and wiring description
architecture netlist of full_add is
signal s,u,v,s2,u2,v2,w2:BIT;
begin
g1:entity WORK.Not1(ex1) port map(a,s);
g2:entity WORK.Not1(ex1) port map(b,u);
g3:entity WORK.Not1(ex1) port map(c,v);
g4:entity WORK.And2(ex1) port map(s,u,c,s2);
g5:entity WORK.And2(ex1) port map(s,b,v,u2);
g6:entity WORK.And2(ex1) port map(a,u,v,v2);
g7:entity WORK.And2(ex1) port map(a,b,v,w2);
g8:entity WORK.Or2(ex1) port map (s2,u2,v2,w2,h);
end architecture netlist;