2

I'm trying to implement a structured read port to Mem:

class TagType() extends Bundle()
{
    import Consts._

    val valid = Bool()
    val dirty = Bool()
    val tag   = UInt(width = ADDR_MSB - ADDR_LSB + 1)
}

object TagType
{
    def apply() = new TagType()
}

val tag_read   = TagType()
//val tag_read   = Reg(TagType())
val tag_read_port   = UInt(width = TagType().getWidth)
val tag_ram    = Mem(UInt(width = TagType().getWidth), num_lines , seqRead = false )

when (tag_read) {
    tag_read_port   := tag_ram(line_no)
    tag_read.toBits := tag_read_port

}

When I use combinational 

val tag_read   = TagType()

instead of sequential

val tag_read   = Reg(TagType())

I get errors

Cache.scala:39: error: NO DEFAULT SPECIFIED FOR WIRE: /*? in class cache.Cache*/ Chisel.Bool(width=1, connect to 0 inputs: ()) in component class cache.Cache in class cache.TagType
Cache.scala:40: error: NO DEFAULT SPECIFIED FOR WIRE: /*? in class cache.Cache*/ Chisel.Bool(width=1, connect to 0 inputs: ()) in component class cache.Cache in class cache.TagType
Cache.scala:41: error: NO DEFAULT SPECIFIED FOR WIRE: /*? in class cache.Cache*/ Chisel.UInt(width=28, connect to 0 inputs: ()) in component class cache.Cache in class cache.TagType

What is the meaning of this error message?

The second question:

Is it possible to have a structured red port a la SystemVerilog, i.e. read directly

tag_read.toBites   := tag_ram(line_no)

instead of

    tag_read_port   := tag_ram(line_no)
    tag_read.toBits := tag_read_port

Thanks!

4

1 回答 1

2

What do lines do 39/40/41 correspond to?

What does "when (tag_read)" mean? Shouldn't you be using a Bool() inside the when statement and not a object?

What is "line_no"? (sequential reads are performed by registering the address).

What are you trying to accomplish with tag_read = Reg(TagType())... [edited] you're creating a register of type TagType, not a node with values associated with it. Thus I suspect the error is that there is no default/initial value for that register if "tag_read_cond" is not true. Using Reg(init=something) will probably fix the error [end edits].

I'd probably lose the object TagType code. I'm not sure what you're trying to do with it. This code will declare a tagType and give it a set of default values:

val tag_read   = new TagType()
tag_read.valid := Bool(false)
tag_read.dirty := Bool(false)
tag_read.tag := UInt(0)

val tag_ram    = Mem(new TagType(), num_lines , seqRead = false )

when (tag_read_cond) {
    tag_read := tag_ram(line_no)
}

Chisel gets angry if your variables do not have default values (i.e., there is a path through your logic in which a variable will not get set, since Chisel does not support X's/don't cares).

Although you can ditch most of that code and probably just write this if you don't mind the extra port:

val tag_ram    = Mem(new TagType(), num_lines , seqRead = false )
val tag_read = tag_ram(line_no)

And for sequential memories:

val tag_ram    = Mem(new TagType(), num_lines , seqRead = true )
val tag_read = tag_ram(RegEnable(line_no, tag_read_cond))

Note the address is registered, with an enable condition that can tell the memory only to read it when evaluated to true. The Chisel manual gives more examples/explanations on constructing sequential memories.

于 2013-10-28T10:30:42.810 回答