有人可以告诉我,如何制作 12 位 std_logic_vector 项的移位寄存器?
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1 回答
1
看看下面的例子。VECTOR_WIDTH 是每个 std_logic_vector 中的位数(在您的情况下为 12)。FIFO_DEPTH 是您想要在移位寄存器中的向量数。
library ieee;
use ieee.std_logic_1164.all;
entity vectors_fifo is
generic (
VECTOR_WIDTH: natural := 12;
FIFO_DEPTH: natural := 100
);
port (
clock: in std_logic;
reset: in std_logic;
input_vector: in std_logic_vector(VECTOR_WIDTH-1 downto 0);
output_vector: out std_logic_vector(VECTOR_WIDTH-1 downto 0)
);
end;
architecture rtl of vectors_fifo is
type fifo_memory_type is array (natural range <>) of std_logic_vector;
signal fifo_memory: fifo_memory_type(0 to FIFO_DEPTH-1)(VECTOR_WIDTH-1 downto 0);
begin
process (clock, reset) begin
if reset then
fifo_memory <= (others => (others => '0'));
elsif rising_edge(clock) then
fifo_memory <= input_vector & fifo_memory(0 to FIFO_DEPTH-2);
end if;
end process;
output_vector <= fifo_memory(FIFO_DEPTH-1);
end;
于 2013-10-20T19:35:55.523 回答