verilog - Two input signals at the same always block

Question

I am working with an DE2-70 board and I am trying to use some of it's buttons as inputs. The buttons are activated at 0, and I need to check if two buttons in particular are being pressend separatly, in order to increase/decrease a number.

I tried doing the following, where iKEY are the buttons and position is the number i am trying to modify:

reg [4:0] position;
position = 5'b0;

output wire enable = !(iKEY[3] && iKEY[2]);
always @(posedge enable) begin  
    if(iKEY[3] == 0)
        position = position + 5'b00001;

    if(iKEY[2] == 0)
        position = position - 5'b00001;
end

I tried several differences of this implementation, such as tring to change the ifs conditions or changing the logic function when setting the enable signal, but I always get stuck in some problem. I am new to hardware logic, so maybe I am thinking in it in the wrong way

Edit: If both buttons are pressed at the same time I expect the hardware to neither increment nor decrement the number

score 2 · Accepted Answer

聊天讨论总结：

缺少关键背景信息：
- iKEY是 4 位低电平有效输入。输入源来自物理按键，
- 操作应该发生在 one-cold（one-hot 的倒数）上iKEY，
- 有可用的时钟，例如 50MHziCLK_50

操作意外执行的解决方案：

将所有的全部iKEY移到一个始终块中，并使用 case 语句对操作进行解码。前任：

case(iKEY[3:0]) // one-cold, full-case
  4'b1110: /* operation 0 */
  4'b1101: /* operation 1 */
  4'b1011: /* operation 2 */
  4'b0111: /* operation 3 */
  default: /* default behavior */
endcase

如果iKEY用作时钟事件，则执行按位 NAND 操作：
```
wire enable = ~&iKEY[3:0];
```

如果使用iCLK_50时钟，则添加一个 reg 以监视按钮释放，以确保每次按下按钮一次操作。前任：

if (allow_op) begin // value from past clock event
  /* case statement defined above */
end
// value for next clock event
allow_op = &iKEY[4:0]; // bit-wise AND

score 0 · Accepted Answer

您可能应该在按钮按下时寻找变化。下面的代码查找 iKEY[3] 输入的下降沿。否则，一旦 IKEY 被按下，该计数器就会变成 NUTS 并开始疯狂地递增或递减。

reg iKEY3_LAST;

output wire enable = !(iKEY[3] && iKEY[2]);
always @(posedge enable) begin  
  iKEY3_LAST = iKEY[3];
  if(iKEY[3] == 0 && iKEY3_LAST == 1)
    position = position + 5'b00001;

score 0 · Accepted Answer

首先，您在信号位置上有一个组合循环。当 enable=1 时，位置会改变，然后一次又一次地改变。在这种情况下，模拟通常会卡住，至于现实世界，这取决于您的工具如何实现它；我想他们中的大多数人只会打破循环。在日志中查找任何错误或警告。你希望位置是一个翻牌，所以它不会是一个循环，而是每个时钟周期都会增加 1：

always @(posedge clock or posedge reset)
if (reset)
   position <= 5'h0;
else
   position <= position + iKEY[3] - iKey[2];

现在您必须考虑到按钮会引入弹跳效果。在这里查看更多信息。您可能想要实现数字开关去抖动。

正如 Russell 所写，您可能会考虑仅在按钮的下降沿更改位置，否则计数器会像疯了一样上溢/下溢。

verilog - Two input signals at the same always block

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