vhdl - JK FlipFlop 代码调试

Question

以下是 JK FlipFlop 的代码：-

entity jkasync is
Port ( j : in std_logic;
       k : in std_logic;
       r : in std_logic;
       clk : in std_logic;
       q : inout std_logic);
 end jkasync;

architecture Behavioral of jkasync is
signal s: std_logic_vector(1 downto 0);
s <= j&k;
begin

  process (j,k,r,clk)
  begin

        if (r='1') then
        q<='0';
        elsif (falling_edge(clk)) then
        case    s is
        when "00" =>q<=q;
        when "01" =>q<='0';
        when "10" =>q<='1';
        when "11" =>q<= not q;
        when others =>q<='0';
        end case;
        end if;
    end process;


  end Behavioral;

我收到以下错误：-

第 21 行。解析错误，意外 IDENTIFIER

第 21 行在哪里s<=j&k; 所以请帮助我更正这段代码的语法，并告诉我这里有什么问题。谢谢你。

Answer 1

知道了。

新信号在架构主体中初始化，但值在流程主体中定义。

所以将第 21 行移到进程内。

正确代码：-

   architecture Behavioral of jkasync is
  signal s: std_logic_vector(1 downto 0);

  begin
  s <= j&k;
  process (j,k,r,clk)
  begin

        if (r='1') then
        q<='0';
        elsif (falling_edge(clk)) then
        case    s is
        when "00" =>q<=q;
        when "01" =>q<='0';
        when "10" =>q<='1';
        when "11" =>q<= not q;
        when others =>q<='0';
        end case;
        end if;
    end process;


        end Behavioral;