0

嗨,我在使用 handel-c 显示静态图像时遇到问题,通过 DE2-115 VGA 创建测试模式。

由于某种原因,我无法将图像输出到显示器。

这是我的 tpad.hcc 代码:

#include "tpad.hch"
macro proc lcd_driver( lcd ) {
unsigned 24 colour;
unsigned 1 de;

interface bus_out() tpad_RGB( unsigned 24 clr = colour )

    //Post pin for RGB color
    //with {data = {"V27","U28","U27","R28","R27","V26",
    //"T22","T21","R23","R22","R21","P21",
    //"J26","L28","V25","V22","U22","V28"},
with {data = {"D12","D11","C12","A11","B11","C11","A10","B10", //BLUE
    "C9","F10","B8","C8","H12","F8","G11","G8",             //GREEN
    "H10","H8","J12","G10","F12","D10","E11","E12"}, //RED
standard = "LVCMOS33"};

interface bus_out() tpad_control( unsigned 3 ctrl = (!__clock) @ 1 @de)
with {data = {"C13","F11","A12", "G13","C10"},
standard = "LVCMOS33"};

 //VHDL driver
 //entity vga_controller is
 //port (
 //     pixel_clk   :   IN STD_LOGIC;   --pixel clock at frequency of VGA mode being used
//      reset_n     :   IN STD_LOGIC;   --active low asycnchronous reset
//      h_sync      :   OUT STD_LOGIC;  --horiztonal sync pulse
//      v_sync      :   OUT STD_LOGIC;  --vertical sync pulse
//      disp_ena    :   OUT STD_LOGIC;  --display enable ('1' = display time, '0' = blanking time)
//      column      :   OUT INTEGER;    --horizontal pixel coordinate
//      row         :   OUT INTEGER;    --vertical pixel coordinate
//      n_blank     :   OUT STD_LOGIC;  --direct blacking output to DAC
//      n_sync      :   OUT STD_LOGIC --sync-on-green output to DAC
//    );  
//END vga_controller;

interface vga_controller( unsigned 11 row, unsigned 11 column, unsigned 1 disp_ena,
                             unsigned 1 h_sync, unsigned 1 v_sync, unsigned 1 n_sync,
                            unsigned 1 n_blank)

            tpad_lcd( unsigned 1 pixel_clk = __clock, unsigned 1 reset_n = 0)
    with {busformat = "B[I]"};

do par {
    colour = lcd.r @ lcd.g @ lcd.b; // Synchronise LCD output signals
    //de = !lcd.nb;
    de = 1;

    lcd.x = tpad_lcd.row;
    lcd.y = tpad_lcd.column;
    lcd.hs = tpad_lcd.h_sync;
    lcd.vs = tpad_lcd.v_sync;
    lcd.ns = tpad_lcd.n_sync;
    lcd.nb = tpad_lcd.n_blank;
    lcd.de = 1;


} while (1);
}

我的 tpad.hch:

typedef struct {
signal unsigned 11 x, y; // Position on display
signal unsigned 8 r, g, b; // Colour to display
signal unsigned 1 hs, vs, ns, nb, de; // syncronisation signals
} lcd_data;
macro proc lcd_driver( lcd );

这是我的 demo.hcc:

#include "tpad.hch"

set family = AlteraCycloneIII; /* Really a Cyclone IV */
set part = "EP4CE115F29C7";
interface bus_in (unsigned 1 pin) clock_pin () with {data = {"Y2"}};
interface altpll (unsigned 5 clk with {clockport = 1})
pll (unsigned 2 inclk = 0 @ clock_pin.pin) 
with {
busformat = "B[N:0]",
properties = {
{"bandwidth_type", "AUTO"},
{"clk0_divide_by", "5"},
{"clk0_duty_cycle", "50"},
{"clk0_multiply_by", "4"},
{"clk0_phase_shift", "0"},
{"compensate_clock", "CLK0"},
{"inclk0_input_frequency", "20000"},
{"intended_device_family", "Cyclone IV E"},
{"lpm_hint", "CBX_MODULE_PREFIX=pll"},
{"lpm_type", "altpll"},
{"operation_mode", "NORMAL"},
{"pll_type", "AUTO"},
{"port_clk0", "PORT_USED"},
{"width_clock", "5"}},
bind = 1};

set clock = internal pll.clk[0];

void main( void ) {
    lcd_data lcd;
par {
lcd_driver( lcd );

do par {
lcd.r = lcd.x[7:0]; // Generate a simple test pattern
lcd.g = lcd.y[7:0];
lcd.b = (lcd.x + lcd.y)[9:2];


} while (1);
}
}

这是我的 VHDL 代码:

--------------------------------------------------------------------------------
--
--   FileName:         vga_controller.vhd
--   Dependencies:     none
--   Design Software:  Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY
--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
--   Version History
--   Version 1.0 05/10/2013 Scott Larson
--     Initial Public Release
--    
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY vga_controller IS
    GENERIC(
        h_pulse     :   INTEGER := 128;     --horiztonal sync pulse width in pixels
        h_bp        :   INTEGER := 88;      --horiztonal back porch width in pixels
        h_pixels    :   INTEGER := 800;     --horiztonal display width in pixels
        h_fp        :   INTEGER := 40;      --horiztonal front porch width in pixels
        h_pol       :   STD_LOGIC := '1';       --horizontal sync pulse polarity (1 = positive, 0 = negative)
        v_pulse     :   INTEGER := 4;           --vertical sync pulse width in rows
        v_bp        :   INTEGER := 23;          --vertical back porch width in rows
        v_pixels    :   INTEGER := 600;     --vertical display width in rows
        v_fp        :   INTEGER := 1;           --vertical front porch width in rows
        v_pol       :   STD_LOGIC := '1');  --vertical sync pulse polarity (1 = positive, 0 = negative)
    PORT(
        pixel_clk   :   IN      STD_LOGIC;  --pixel clock at frequency of VGA mode being used
        reset_n     :   IN      STD_LOGIC;      --active low asycnchronous reset
        h_sync      :   OUT STD_LOGIC;  --horiztonal sync pulse
        v_sync      :   OUT STD_LOGIC;  --vertical sync pulse
        disp_ena        :   OUT STD_LOGIC;  --display enable ('1' = display time, '0' = blanking time)
        column      :   OUT STD_LOGIC_vector (10 downto 0);     --horizontal pixel coordinate
        row         :   OUT STD_LOGIC_vector (10 downto 0); --vertical pixel coordinate
        n_blank     :   OUT STD_LOGIC;  --direct blacking output to DAC
        n_sync      :   OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;

ARCHITECTURE behavior OF vga_controller IS
    CONSTANT    h_period    :   INTEGER := h_pulse + h_bp + h_pixels + h_fp;  --total number of pixel clocks in a row
    CONSTANT    v_period    :   INTEGER := v_pulse + v_bp + v_pixels + v_fp;  --total number of rows in column
BEGIN

    n_blank <= '1';  --no direct blanking
    n_sync <= '0';   --no sync on green

    PROCESS(pixel_clk, reset_n)
        VARIABLE h_count    :   INTEGER RANGE 0 TO h_period - 1 := 0;  --horizontal counter (counts the columns)
        VARIABLE v_count    :   INTEGER RANGE 0 TO v_period - 1 := 0;  --vertical counter (counts the rows)
    --VARIABLE h_count : unsigned (7 downto 0) := "00000000";
    --VARIABLE v_count : unsigned (7 downto 0) := "00000000";

    BEGIN

        IF(reset_n = '0') THEN      --reset asserted
            h_count := 0;               --reset horizontal counter
            v_count := 0;               --reset vertical counter
            h_sync <= NOT h_pol;        --deassert horizontal sync
            v_sync <= NOT v_pol;        --deassert vertical sync
            disp_ena <= '0';            --disable display
            column <= "00000000000";                --reset column pixel coordinate
            row <= "00000000000";                   --reset row pixel coordinate

        ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN

            --counters
            IF(h_count < h_period - 1) THEN     --horizontal counter (pixels)
                h_count := h_count + 1;
            ELSE
                h_count := 0;
                IF(v_count < v_period - 1) THEN --veritcal counter (rows)
                    v_count := v_count + 1;
                ELSE
                    v_count := 0;
                END IF;
            END IF;

            --horizontal sync signal
            IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
                h_sync <= NOT h_pol;        --deassert horiztonal sync pulse
            ELSE
                h_sync <= h_pol;            --assert horiztonal sync pulse
            END IF;

            --vertical sync signal
            IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
                v_sync <= NOT v_pol;        --deassert vertical sync pulse
            ELSE
                v_sync <= v_pol;            --assert vertical sync pulse
            END IF;

            --set pixel coordinates
            IF(h_count < h_pixels) THEN     --horiztonal display time
                --column <= h_count;            --set horiztonal pixel coordinate
                column <= std_logic_vector(to_unsigned(h_count, column'length)); --set horiztonal pixel coordinate
            END IF;
            IF(v_count < v_pixels) THEN --vertical display time
                --row <= v_count;               --set vertical pixel coordinate
                row <= std_logic_vector(to_unsigned(v_count, column'length));    --set vertical pixel coordinate
            END IF;

            --set display enable output
            IF(h_count < h_pixels AND v_count < v_pixels) THEN      --display time
                disp_ena <= '1';                                                --enable display
            ELSE                                                                    --blanking time
                disp_ena <= '0';                                                --disable display
            END IF;

        END IF;
    END PROCESS;

END behavior;
4

0 回答 0