0

我是 VHDL 新手，尝试编译代码时出现以下错误：

错误 (10517)：vga_controller.vhd(60) 处的 VHDL 类型不匹配错误：std_logic 类型与整数文字不匹配错误 (10327)：vga_controller.vhd(60) 处的 VHDL 错误：无法确定运算符“-”的定义" -- 找到 0 个可能的定义

似乎问题出在 h_count 上，在我设置为 STD_lOGIC 之前，我将其设置为 INTEGER，它抱怨如下：

错误 (10476)：vga_controller.vhd(104) 处的 VHDL 错误：标识符“h_count”的类型与其作为“std_logic_vector”类型的用法不一致

因此我将其更改为 STD_LOGIC 但它只是给了我另一个错误消息。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY vga_controller IS
GENERIC(
h_pulse     :   INTEGER := 128;     --horiztonal sync pulse width in pixels
    h_bp        :   INTEGER := 88;      --horiztonal back porch width in pixels
    h_pixels    :   INTEGER := 800;     --horiztonal display width in pixels
    h_fp        :   INTEGER := 40;      --horiztonal front porch width in pixels
    h_pol       :   STD_LOGIC := '1';       --horizontal sync pulse polarity (1 = positive, 0 = negative)
    v_pulse     :   INTEGER := 4;       
v_bp        :   INTEGER := 23;          --vertical back porch width in rows
    v_pixels    :   INTEGER := 600;     --vertical display width in rows
    v_fp        :   INTEGER := 1;           --vertical front porch width in rows
    v_pol       :   STD_LOGIC := '1');  --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
    pixel_clk   :   IN      STD_LOGIC;  --pixel clock at frequency of VGA mode being used
    reset_n     :   IN      STD_LOGIC;      --active low asycnchronous reset
    h_sync      :   OUT STD_LOGIC;  --horiztonal sync pulse
    v_sync      :   OUT STD_LOGIC;  --vertical sync pulse
    disp_ena        :   OUT STD_LOGIC;  --display enable ('1' = display time, '0' = blanking time)
    column      :   OUT STD_LOGIC_VECTOR (10 downto 0);     --horizontal pixel coordinate
    row         :   OUT STD_LOGIC_VECTOR (10 downto 0); --vertical pixel coordinate
    n_blank     :   OUT STD_LOGIC;  --direct blacking output to DAC
    n_sync      :   OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;

ARCHITECTURE behavior OF vga_controller IS
CONSTANT    h_period    :   INTEGER := h_pulse + h_bp + h_pixels + h_fp;  --total number of pixel clocks in a row
CONSTANT    v_period    :   INTEGER := v_pulse + v_bp + v_pixels + v_fp;  --total number of rows in column
BEGIN

BEGIN

    n_blank <= '1';  --no direct blanking
    n_sync <= '0';   --no sync on green

    PROCESS(pixel_clk, reset_n)
        VARIABLE h_count    :   STD_LOGIC RANGE 0 TO h_period - 1 := 0;  --horizontal counter (counts the columns)
        VARIABLE v_count    :   STD_LOGIC RANGE 0 TO v_period - 1 := 0;  --vertical counter (counts the rows)

    BEGIN

        IF(reset_n = '0') THEN      --reset asserted
            h_count := 0;               --reset horizontal counter
            v_count := 0;               --reset vertical counter
            h_sync <= NOT h_pol;        --deassert horizontal sync
            v_sync <= NOT v_pol;        --deassert vertical sync
            disp_ena <= '0';            --disable display
            column <= "00000000000";                --reset column pixel coordinate
            row <= "00000000000";                   --reset row pixel coordinate

        ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN

            --counters
            IF(h_count < h_period - 1) THEN     --horizontal counter (pixels)
                h_count := h_count + 1;
            ELSE
                h_count := 0;
                IF(v_count < v_period - 1) THEN --veritcal counter (rows)
                    v_count := v_count + 1;
                ELSE
                    v_count := 0;
                END IF;
            END IF;

            --horizontal sync signal
            IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
                h_sync <= NOT h_pol;        --deassert horiztonal sync pulse
            ELSE
                h_sync <= h_pol;            --assert horiztonal sync pulse
            END IF;

            --vertical sync signal
            IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
                v_sync <= NOT v_pol;        --deassert vertical sync pulse
            ELSE
                v_sync <= v_pol;            --assert vertical sync pulse
            END IF;

            --set pixel coordinates
            IF(h_count < h_pixels) THEN     --horiztonal display time
                column <= h_count;          --set horiztonal pixel coordinate
            END IF;
            IF(v_count < v_pixels) THEN --vertical display time
                row <= v_count;             --set vertical pixel coordinate
            END IF;

            --set display enable output
            IF(h_count < h_pixels AND v_count < v_pixels) THEN      --display time
                disp_ena <= '1';                                                --enable display
            ELSE                                                                    --blanking time
                disp_ena <= '0';                                                --disable display
            END IF;

        END IF;
    END PROCESS;

END behavior;
4

3 回答 3

0

如果您想要一个位向量来表示一个数字，请使用该ieee.numeric_std库，然后使用unsignedand/orsigned类型。和/或使用integers。 不要std_logic_vector用来表示数字。

于 2013-09-26T13:19:26.527 回答
0

您的问题是您正在混合整数和 std_logic_vector 类型。

例如，您将h_count整数分配给列std_logic_vector 而不进行类型转换。您的线路：

column <= h_count;

应该：

column <= std_logic_vector(to_unsigned(h_count, column'length));

这将h_count类型转换为与column宽度相同的无符号，然后将其转换为 std_logic_vector 类型。每次将整数转换为 std_logic_vector 时也是如此。

要反过来将 std_logic_vector 转换为整数，请使用以下示例，假设它是无符号的：

h_count <= to_integer(unsigned(column));
于 2013-09-26T00:26:58.960 回答
0

您提供的错误消息中的行号与代码片段不匹配，并且您的架构有重复的 BEGIN。

回到最初的设计规范：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY vga_controller IS
    GENERIC(
        h_pulse     :   INTEGER := 128;     --horiztonal sync pulse width in pixels
        h_bp        :   INTEGER := 88;      --horiztonal back porch width in pixels
        h_pixels    :   INTEGER := 800;     --horiztonal display width in pixels
        h_fp        :   INTEGER := 40;      --horiztonal front porch width in pixels
        h_pol       :   STD_ULOGIC := '1';  --horizontal sync pulse polarity (1 = positive, 0 = negative)
        v_pulse     :   INTEGER := 4;       
        v_bp        :   INTEGER := 23;       --vertical back porch width in rows
        v_pixels    :   INTEGER := 600;      --vertical display width in rows
        v_fp        :   INTEGER := 1;        --vertical front porch width in rows
        v_pol       :   STD_ULOGIC := '1'    --vertical sync pulse polarity (1 = positive, 0 = negative)
    );
PORT(
        pixel_clk   :   IN  STD_LOGIC;  --pixel clock at frequency of VGA mode being used
        reset_n     :   IN  STD_LOGIC;      --active low asycnchronous reset
        h_sync      :   OUT STD_LOGIC;  --horiztonal sync pulse
        v_sync      :   OUT STD_LOGIC;  --vertical sync pulse
        disp_ena    :   OUT STD_LOGIC;  --display enable ('1' = display time, '0' = blanking time)
        column      :   OUT STD_LOGIC_VECTOR (10 downto 0);     --horizontal pixel coordinate
        row         :   OUT STD_LOGIC_VECTOR (10 downto 0); --vertical pixel coordinate
        n_blank     :   OUT STD_LOGIC;  --direct blacking output to DAC
        n_sync      :   OUT STD_LOGIC --sync-on-green output to DAC
    );
END vga_controller;

ARCHITECTURE behavior OF vga_controller IS
CONSTANT    h_period    :   INTEGER := h_pulse + h_bp + h_pixels + h_fp;  --total number of pixel clocks in a row
CONSTANT    v_period    :   INTEGER := v_pulse + v_bp + v_pixels + v_fp;  --total number of rows in column

BEGIN

    n_blank <= '1';  --no direct blanking
    n_sync <= '0';   --no sync on green

frame_counters:
    PROCESS(pixel_clk, reset_n)
        VARIABLE h_count    :   INTEGER RANGE 0 TO h_period - 1 := 0;  --horizontal counter (counts the columns)
        VARIABLE v_count    :   INTEGER RANGE 0 TO v_period - 1 := 0;  --vertical counter (counts the rows)

    BEGIN

        IF(reset_n = '0') THEN      --reset asserted
            h_count := 0;               --reset horizontal counter
            v_count := 0;               --reset vertical counter
            h_sync <= NOT h_pol;        --deassert horizontal sync
            v_sync <= NOT v_pol;        --deassert vertical sync
            disp_ena <= '0';            --disable display
            column <= "00000000000";                --reset column pixel coordinate
            row <= "00000000000";                   --reset row pixel coordinate

        ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN

            --counters
            IF(h_count < h_period - 1) THEN     --horizontal counter (pixels)
                h_count := h_count + 1;
            ELSE
                h_count := 0;
                IF(v_count < v_period - 1) THEN --veritcal counter (rows)
                    v_count := v_count + 1;
                ELSE
                    v_count := 0;
                END IF;
            END IF;

            --horizontal sync signal
            IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
                h_sync <= NOT h_pol;        --deassert horiztonal sync pulse
            ELSE
                h_sync <= h_pol;            --assert horiztonal sync pulse
            END IF;

            --vertical sync signal
            IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
                v_sync <= NOT v_pol;        --deassert vertical sync pulse
            ELSE
                v_sync <= v_pol;            --assert vertical sync pulse
            END IF;

            --set pixel coordinates
            IF(h_count < h_pixels) THEN     --horiztonal display time
                column <= std_logic_vector(to_unsigned(h_count,column'LENGTH));          --set horiztonal pixel coordinate
            END IF;
            IF(v_count < v_pixels) THEN --vertical display time
                row <= std_logic_vector(to_unsigned(v_count,row'LENGTH));             --set vertical pixel coordinate
            END IF;

            --set display enable output
            IF(h_count < h_pixels AND v_count < v_pixels) THEN      --display time
                disp_ena <= '1';                                    --enable display
            ELSE                                                                  --blanking time
                disp_ena <= '0';                                                --disable display
            END IF;

        END IF;
    END PROCESS;

END behavior;

请注意支持整数到 std_logic_vector 转换的更改：

        --set pixel coordinates
        IF(h_count < h_pixels) THEN     --horiztonal display time
            column <= std_logic_vector(to_unsigned(h_count,column'LENGTH));  --set horiztonal pixel coordinate
        END IF;
        IF(v_count < v_pixels) THEN --vertical display time
            row <= std_logic_vector(to_unsigned(v_count,row'LENGTH));    --set vertical pixel coordinate
        END IF;

请注意，这是伪来源，只是为了清晰地分析（确实如此）。

于 2013-09-26T00:33:37.110 回答