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I have a clock which is always active, I have another clock call it "sample" , which is generated from the first clock . I want to generate a delay of "sample" signal by fixed number of cycles of the first clock signal in verilog

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2 回答 2

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使用移位寄存器：

parameter DELAY = number_of_clock_cycles_you_want_to_delay_by;

reg [DELAY-1:0] shift_reg;

always @(posedge clk)
    begin
          shift_reg <= { shift_reg[DELAY-2:0], signal_you_want_to_delay};
    end

assign delayed_signal = shift_reg[DELAY-1];
于 2013-10-02T07:44:05.313 回答
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我认为您需要添加一个倒计时计数器，否则它会一直向左移动而不会结束。

于 2017-06-05T18:19:58.060 回答