signals - Generate a clock delay by fixed cycles number Verilog

Question

I have a clock which is always active, I have another clock call it "sample" , which is generated from the first clock . I want to generate a delay of "sample" signal by fixed number of cycles of the first clock signal in verilog

Answer 1

使用移位寄存器：

parameter DELAY = number_of_clock_cycles_you_want_to_delay_by;

reg [DELAY-1:0] shift_reg;

always @(posedge clk)
    begin
          shift_reg <= { shift_reg[DELAY-2:0], signal_you_want_to_delay};
    end

assign delayed_signal = shift_reg[DELAY-1];

Answer 2

我认为您需要添加一个倒计时计数器，否则它会一直向左移动而不会结束。