注意：D 和filtered_right 应该在图片中连接。
大家好，我很难在图片上创建一个电路。这个想法是有一个旋转结，每向右旋转一次，一些计数器就会增加，每向左旋转一次，它就会减少。当达到某个值时，我希望一些 LED 发光。它的工作原理如下：如果左信号先激活，则向右旋转，否则向左旋转。但是当过滤时，逻辑与代码中的一样。如果有上升沿（如果 D Flip Flop 上的 Q 和 D 不同），并且 D 为“1”，但同时另一个信号为“1”则向右旋转，否则为旋转向左。
我正在使用 Spartan 3AN-Starter Kit FPGA。我在两个单独的实体中描述了过滤器和 DFF，并将它们用作我的主项目中的组件，但是警告不断表明无论我做什么，它们都保持未连接，即使它成功合成。我想知道为什么会这样。
这是电路图、我的 VHDL 代码和警告：
这是主要项目：
--Main project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.all;
entity Demux is
port ( led : OUT std_logic_vector(7 downto 0);
turn_right, turn_left,clk: IN std_logic);
subtype smallint is integer range 0 to 80;
end Demux;
architecture Behavioral of Demux is
component dff
port (set,reset,D,clk: IN std_logic;
Q: OUT std_logic);
end component;
component filter
port (clk,turn_right,turn_left: in std_logic;
filtered_right, filtered_left: out std_logic);
end component;
signal counter: smallint:=0;
signal Q: std_logic;
signal filtered_right: std_logic :='0';
signal filtered_left: std_logic := '0';
signal set: std_logic;
signal reset: std_logic;
begin
set <= '0';
reset <='0';
FF: dff port map (
set=>set,
reset=>reset,
D=>filtered_right,
clk=>clk,
Q=>Q);
filt: filter port map (
turn_right=>turn_right,
turn_left=>turn_left,
filtered_right=>filtered_right,
filtered_left=>filtered_left,
clk=>clk);
compare: process (clk,Q) is
begin
if ((clk'event) and (clk='1')) then
if ((filtered_right /= Q) and (filtered_right='1')) then
if (filtered_left = '1') then
counter <= counter + 1;
elsif (filtered_left = '0') then
counter <= counter - 1;
end if;
end if;
if (counter>80) or (counter<0) then
counter <=0;
end if;
end if;
end process compare;
led(0) <= '1' when counter = 10;
led(1) <= '1' when counter = 20;
led(2) <= '1' when counter = 30;
led(3) <= '1' when counter = 40;
led(4) <= '1' when counter = 50;
led(5) <= '1' when counter = 60;
led(6) <= '1' when counter = 70;
led(7) <= '1' when counter = 80;
end Behavioral;
这是我对 DFF 的实现：
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity dff is
port (D,set,reset,clk: in std_logic;
Q: out std_logic);
end dff;
Architecture behavioral of dff is
begin
dff: process (clk,set,reset,D) is
begin
if ((clk'event) and (clk='1')) then
if (reset='1') then
Q<='0';
elsif (set='1') then
Q<='1';
else
Q<=D;
end if;
end if;
end process dff;
end behavioral;
这是我对过滤器的实现：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity filter is
port (clk,turn_right,turn_left: in std_logic;
filtered_right, filtered_left: out std_logic);
end filter;
architecture Behavioral of filter is
begin
filter: process(clk, turn_right,turn_left) is
variable rotary_conc: std_logic_vector(1 downto 0);
variable filtered_left_temp, filtered_right_temp: std_logic;
begin
if ((clk'event) and (clk='1')) then
rotary_conc:=turn_left & turn_right;
case rotary_conc is
when "00" => filtered_right_temp := '0';
filtered_left_temp := filtered_left_temp;
when "01" => filtered_right_temp := filtered_right_temp;
filtered_left_temp := '0';
when "10" => filtered_right_temp := filtered_right_temp;
filtered_left_temp :='1';
when "11" => filtered_right_temp := '1';
filtered_left_temp := filtered_left_temp;
when OTHERS => filtered_right_temp := filtered_right_temp;
filtered_left_temp := filtered_left_temp;
end case;
filtered_right<=filtered_right_temp;
filtered_left<=filtered_left_temp;
end if;
end process filter;
end Behavioral;
正如您所知，过滤器的存在是因为旋转结的机械性质会产生颤振。该喋喋不休会产生错误的增量/减量。为了避免它 - 我过滤它。
警告：
WARNING:Xst:1290 - Hierarchical block <FF> is unconnected in block <Demux>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <filt> is unconnected in block <Demux>.
It will be removed from the design.
WARNING:Xst:2677 - Node <FF/Q> of sequential type is unconnected in block <Demux>.
WARNING:Xst:2677 - Node <filt/filtered_right_temp> of sequential type is unconnected in block <Demux>.
WARNING:Xst:2677 - Node <filt/filtered_left_temp> of sequential type is unconnected in block <Demux>.