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几天后我的第一个 Verilog 任务到期，无论出于何种原因，这些概念都在逃避我。我不认为我在考虑并行性和硬件或其他方面。

我的问题是我必须使用 sand一起使用几个开关和按钮wire并打开 7 个阵列中的 3 个 LED。我很确定我知道如何进行计算逻辑，但我不知道如何使用assign和wire正确打开所有 3 个 LED，而无需写入 3 个单独的行。这样做感觉不对：

assign Led[0] = output;
assign Led[1] = output;
assign Led[2] = output;

此外，这很奇怪，因为板上有 7 个 LED，而我选择的是 LED 0、2、4。

有人可以告诉我这应该如何以正确的方式工作吗？我们没有教科书，我一直在网上阅读基础知识，但我似乎无法弄清楚这应该如何工作。谢谢！

编辑：这是我当前的代码，但我收到的错误表明没有什么是“驱动的”。是什么赋予了？

module Lab2_1(input [5:0] sw, input btns, output [7:0] Led );

    wire [2:0] leds; 
    wand out; 

    assign leds = {Led[0], Led[2], Led[4]};

    and U1   (out, sw[0], sw[1]);
    and U2   (out,~sw[2],~sw[3]);
    xor U3   (out,sw[4],sw[5]);
    assign   out = btns;
    assign leds[2:0] = {3{out}};

endmodule

错误：

ERROR:PhysDesignRules:368 - The signal <Led<3>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<4>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<5>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<6>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<7>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<0>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<1>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<2>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:10 - The network <Led<3>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<4>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<5>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<6>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<7>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<0>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<1>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<2>_OBUF> is completely unrouted.
ERROR:Bitgen:25 - DRC detected 16 errors and 0 warnings.  Please see the
   previously displayed individual error or warning messages for more details.
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1 回答 1

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您已经拥有的看起来非常好，但如果您想在一行中完成，您可以使用连接和/或复制运算符来分配Led. 这两个语句都等效于您的代码示例：

assign Led[2:0] = {output, output, output};

或者

assign Led[2:0] = {3{output}};

我不知道这些是否比你已经拥有的更好或更合适，但只是写它们来展示一些可以做的例子。

=== 编辑 ===

您收到错误是因为您没有驱动Led.

  1. 这向后看：assign leds = {Led[0], Led[2], Led[4]};
    Led是模块的输出，所以它应该被分配给，这意味着它应该在等号的左侧，所以我猜这应该看起来像assign {Led[0], Led[2], Led[4]} = leds;

  2. 您的模块有一个 8 位 LED 输出，但您只分配了 3 位。您应该将其他 5 位分配给常量 1 或 0。

于 2013-09-16T03:00:54.167 回答