2

I have code with various parts which can be enabled or disabled with macros. This can be done with #ifdef/#endif in the code, with -D options in the makefile and by calling make with setting the macro. Example:

make DOMP=-DUSE_OMP

In the makefile

calco.o: calco.cpp calco.h
    $(CC) calco.cpp -o calco.o $(DOMP)

in the code

#ifdef USE_OMP
#pragma omp parallel for
#endif
    for (i =0; i < N; i++) {
       ...
    }

I have quite a few of possible macros that can be set and would like to be able to have these set simply by making a different target. For example

make calc_abc

would build my application using a particular set of macros, whereas

make calc_xyz

would do this with a different set of macros.

I tried different approaches in my makefile, but found nothing that worked. Is something like this possible at all?

4

1 回答 1

5

您可以为此使用特定于目标的变量。特定于目标的变量的特征之一是它们被其先决条件继承。所以：

calc_abc : CPPFLAGS += -DUSE_ABC
calc_xyz : CPPFLAGS += -DUSE_XYZ

calc_abc : calc
calc_xyz : calc

calc: foo.o bar.o

当然，这里的技巧是你必须确保make clean在这些不同类型的构建之间运行，否则你会得到一个以不同方式构建的对象的混杂。如果您认为您通常希望以不同的方式构建并共存的东西，那么通常您会选择根据类型将目标文件放在不同的子目录中。这样他们就不会互相干扰了。

于 2013-09-11T13:57:22.667 回答