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我正在尝试在verilog中编写一个波纹进位加法器。

module half_adder(a,b,sum,carry);
   input a,b;
   output sum,carry;
   assign sum=a^b;
   assign carry=a&b;
endmodule


module full_adder(a,b,cin,sum,cout);
   input a,b,cin;
   output sum,cout;
   wire   t1,t2;
   half_adder h(a,b,t1,t2);
   assign cout=t1&cin;
   assign sum=t1^cin;
   assign cout=t2|cout;
endmodule // full_adder

module ripple_carry_adder(input1,input2,answer);
   input [31:0] input1,input2;
   output [31:0] answer;
   integer       carry,t;
   genvar        i;
   initial begin
     assign carry=1'b0;
   end

   for(i=0;i<=31;i=i+1)
     begin
        full_adder f(input1[i],input2[i],carry,answer[i],t);
        assign carry=t;
     end
endmodule

但是，当我使用 iverilog 模拟器进行编译时，会显示以下错误日志（已删除重复错误）：

   ripple_carry_adder.v:28: warning: Couldn't build unique name for unnamed generate block - using internal name $gen1
    ripple_carry_adder.v:30: warning: Port 3 (cin) of full_adder expects 1 bits, got 32.
    ripple_carry_adder.v:30:        : Pruning (signed) 31 high bits of the expression.
    ripple_carry_adder.v:30: error: reg t; cannot be driven by primitives or continuous assignment.
    ripple_carry_adder.v:30: error: Output port expression must support continuous assignment.
    ripple_carry_adder.v:30:      : Port cout of full_adder is connected to t
    ripple_carry_adder.v:31: error: reg carry; cannot be driven by primitives or continuous assignment.
    ripple_carry_adder.v:28: warning: Couldn't build unique name for unnamed generate block - using internal name $gen1
    ripple_carry_adder.v:30: warning: Port 3 (cin) of full_adder expects 1 bits, got 32.
    ripple_carry_adder.v:30:        : Pruning (signed) 31 high bits of the expression.
    ripple_carry_adder.v:30: error: reg t; cannot be driven by primitives or continuous assignment.
    ripple_carry_adder.v:30: error: Output port expression must support continuous assignment.
    ripple_carry_adder.v:30:      : Port cout of full_adder is connected to t
    ripple_carry_adder.v:31: error: reg carry; cannot be driven by primitives or continuous assignment.

我哪里错了？

编辑：现在使用生成语句。仍然对进位的类型有疑问。

module ripple_carry_adder(input1,input2,answer);
   input [31:0] input1,input2;
   output [31:0] answer;
   wire          carry;
   wire          t;

   initial begin
     carry=1'b0;
   end
   genvar        i;
   generate for(i=0;i<=31;i=i+1)
     begin
        full_adder f(input1[i],input2[i],carry,answer[i],t);
        carry=t;
     end endgenerate
endmodule
4

2 回答 2

2

您应该摆脱初始块。你可以放下t。然后使用生成块：

   wire [31:0] carry;
   genvar i;
   full_adder f(input1[0],input2[0],1'b0,answer[0],carry[0]);
   generate // optional in IEEE std 1364-2005 and IEEE std 1800
   for(i=1;i<=31;i=i+1)
     begin
        full_adder f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
        //assign carry=t;
     end
   endgenerate
endmodule

或者，与旧的 1364-1995 风格一起使用的东西：

full_adder f[31:0](input1[31:0],input2[31:0],{carry[30:0],1'b0},answer[31:0],carry[31:0]);
于 2013-08-15T18:51:20.337 回答
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  1. assign语句不能在语句块内使用。只要有begin/end块，语句的左侧就会在不使用assign关键字的情况下设置。例如：

    initial begin
     carry = 1'b0
end

  2. 您不能在程序块或 for 循环（例如full_adder）内实例化模块，您需要使用 generate 语句代替。您声明了一个 genvar，所以我认为您打算这样做，但您似乎没有生成语句。

  3. 您不能reg/integer从模块的输出驱动类型，reg/integers只能从程序块驱动。将类型t从a 更改integer为 a wire[31:0]。

于 2013-08-15T18:10:27.977 回答