vhdl - 使用泛型参数作为端口数组长度

Question

我想做的事：

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
      -- ...
      h : in array(0 to NTAPS-1) of std_logic_vector(15 downto 0) );
end FIRfitler;

但是上面的语法h是不正确的。

这个问题类似： How to specify an integer array as generic in VHDL? 但这并没有让我在实例化时获得一般的点击次数。这甚至可能吗？

Answer 1

If you declare an unconstrained array type in a package, then you can constrain the array based on a generic, as shown in the code below:

library ieee; use ieee.std_logic_1164.all;

package FIRfilter_pkg is
  type x_t is array(natural range <>) of std_logic_vector(15 downto 0);
end package;


library ieee; use ieee.std_logic_1164.all;
library work; use work.FIRfilter_pkg.all;

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
     x : in x_t(0 to NTAPS-1);
     z : out std_logic_vector(15 downto 0) );  -- For simple example below
end FIRfilter;


library ieee; use ieee.numeric_std.all;

architecture syn of FIRfilter is
begin
  z <= std_logic_vector(unsigned(x(0)) + unsigned(x(1)));  -- Usage example
end architecture;