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Simply put I want to give a name to a rule in my Makefile:

A.ext : B.ext
    compute A.ext from B.ext

so that I get something like this:

.PHONY : my_rule
A.ext : my_rule
my_rule : B.ext
    compute A.ext from B.ext

But this is not yet equivalent to the first, since my_rule is always executed even if B.ext hasn't changed. How can I achieve equivalence?

This is the trimmed output of make -d:

Considering target file `A.ext'.
  Considering target file `my_rule'.
   File `my_rule' does not exist.
    Considering target file `B.ext'.
     Finished prerequisites of target file `B.ext'.
    No need to remake target `B.ext'.
   Finished prerequisites of target file `my_rule'.
  Must remake target `my_rule'.

(The reason I want this is that I have another rule C.ext :| my_rule.)

4

1 回答 1

1 
.PHONY : my_rule
my_rule: A.ext
A.ext : B.ext
    compute A.ext from B.ext

或者更好：

.PHONY : my_rule
my_rule: A.ext
A.ext : B.ext
    compute $@ from $<
于 2013-08-12T13:02:14.983 回答