1

I have a makefile with four targets. Two of these targets can be duplicated so that there can possibly be many of them that are required to run as prerequisites (they are double-colon targets). Two of the targets are match-anything rules. Unfortunately, it's not working at all like I'd expect it to. I started with this:

.PHONY:
build_%: pre_build post_build _internal_%
        @echo "4. $@: $^"

.PHONY: pre_build
pre_build::
        @echo "1. $@: $^"

.PHONY: _internal_%
_internal_%:
        @echo "2. $@: $^"

.PHONY: post_build
post_build::
        @echo "3. $@: $^"

That gave me this output:

make build_foo
1. pre_build: 
3. post_build: 
2. _internal_foo: 
4. build_foo: pre_build _internal_foo post_build

If I am explicit about prereqs, like this:

.PHONY:
build_%: pre_build post_build _internal_%
        @echo "4. $@: $^"

.PHONY: pre_build
pre_build::
        @echo "1. $@: $^"

.PHONY: _internal_%
_internal_%: pre_build
        @echo "2. $@: $^"

.PHONY: post_build
post_build:: _internal_%
        @echo "3. $@: $^"

Instead I get this:

make build_foo
1. pre_build: 
make: *** No rule to make target `pre_build'.  Stop.

What do I need to do to make a dependency work like this? I am using GNU Make 3.81.

4

1 回答 1

0

这似乎是 GNU Make 3.81 中的一个真正的错误。

我建议这种解决方法：

define prebuild
@echo "1. pre_build: $^"
endef

define postbuild
@echo "3. post_build: $^"
endef

.PHONY:
build_%: _internal_%
        @echo "4. $@: $^"

.PHONY: _internal_%
_internal_%:
        $(prebuild)
        @echo "2. $@: $^"
        $(postbuild)

# pre_build and post_build are not used here, but may still be used elsewhere

.PHONY: pre_build
pre_build::
    $(prebuild)

.PHONY: post_build
post_build::
        $(postbuild)
于 2013-08-10T02:28:03.270 回答