arrays - 在两个 VHDL 模块之间共享“数组数组”

Question

我有一个在两个 VHDL 模块之间共享“数组数组”的问题。

我在 VHDL 子模块中声明了一个“数组数组”，如下所示，

type avg_log is array (0 to 31) of std_Logic_vector(19 downto 0); 
signal V1 :avg_log :=(others=>others=>'0');

我想将所有元素发送V1()()到顶部模块，我尝试使用 PORT & GENERIC，但收到一条错误消息。

谁能帮帮我吗？

Answer 1

You need to define your type in a package, and then include it in both entities via use like this:

library ieee;
use ieee.std_logic_1164.all;

package p_avg is
    type avg_log is array (0 to 31) of std_Logic_vector(19 downto 0);
end package p_avg;

and then in your entity

use work.p_avg.all;
entity my_e is
    port(
      ...
      V1 : out avg_log := (others => (others => '0'));
      ...
    );
end entity;

and then use it in your port map in the surrounding architecture (where the package also has to be included)... There are other ways, but this is the way I would suggest...

Answer 2

下面的整个示例，定义了 p_avg 包（如 BennyBarns 建议的那样）、my_e 子模块 my_e 和 tb 顶级模块；可以用 ModelSim 编译：

library ieee;
use ieee.std_logic_1164.all;

package p_avg is
  type avg_log is array (0 to 31) of std_logic_vector(19 downto 0);
end package p_avg;



library ieee;
use ieee.std_logic_1164.all;
library work;
use work.p_avg.all;

entity my_e is
  port(
    v1_o : out avg_log);
end entity;

architecture sim of my_e is
begin
  v1_o <= (others => (others => '0'));
end architecture;



library ieee;
use ieee.std_logic_1164.all;
library work;
use work.p_avg.all;

entity tb is
end entity;

architecture sim of tb is
  signal v1 : avg_log;
begin

  my_e_1 : entity work.my_e
    port map(
      v1_o => v1);

end architecture;