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我有两个二维数组：

type array1x1D is array (0 to 10) of std_logic_vector(0 to 10); -- Array of arrays
type array2D is array (0 to 10, 0 to 10) of std_logic; -- Real 2D array

如何访问std_logic_vectors前者的范围和后者的范围？我当然可以使用变量来跟踪它们的大小，但我宁愿避免这种情况。我正在尝试使用GENERATE语句遍历数组。

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2 回答 2

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数组1x1D：

VHDL-2002：std_logic_vector(0 downto 10)如果要获取此部分的范围，则需要子类型，因此将类型拆分为：

subtype array1x1D_element is std_logic_vector(0 to 10);
type array1x1D is array (0 to 10) of array1x1D_element; -- Array of arrays

然后你可以做array1x1D_element'range。

VHDL-2008：使用添加的'element属性（可能用于该目的:-)，然后编写array1x1D'element'range.

数组2D：

通过索引访问不同的维度 to 'range，因此使用array2D'range(1)和array2D'range(2)。

于 2013-07-23T16:00:43.800 回答
3 
entity test1 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a1 of test1 is
    type array1x1D is array (0 to 10) of std_logic_vector(0 to 10); -- Array of arrays
    type array2D is array (0 to 10, 0 to 5) of std_logic; -- Real 2D array
    signal s1 : array1x1D;
begin
    name : process is
    begin
        report "array1x1D(0)'length:" & integer'image(s1(0)'length);
        report "array2D'length(1):" & integer'image(array2D'length(1));
        report "array2D'length(2):" & integer'image(array2D'length(2));
        wait;
    end process name;
end architecture a1;

产生：

# run -all
# ** Note: array1x1D(0)'length:11
#    Time: 0 ns  Iteration: 0  Instance: /test1
# ** Note: array2D'length(1):11
#    Time: 0 ns  Iteration: 0  Instance: /test1
# ** Note: array2D'length(2):6
#    Time: 0 ns  Iteration: 0  Instance: /test1
#

如果没有该类型的中间信号/常数/变量，我无法立即找到一种方法来计算一维数组的向量元素的长度......

于 2013-07-23T16:07:23.433 回答