verilog - Verilog 16 bit overflow for 32 bit reg

Question

I have declared two input [32:0] ports in1,in2 and an output reg [32:0] out

in the always block, the code goes as follows: out=in1+in2;

now it works fine for add, but when in1=0 and in2=-1, out is always 0x0000ffff instead of 0xffffffff

I tried declaring integer [32:0] types but I don't think am doing it properly.

(transcribed from comment:)

module adder(out, in1, in2, sub);
output reg[31:0] out;
input [31:0] in1, in2;
input [4:0] sub;

always @(*) begin
 case (sub)
  `ALU_ADD: begin out=alutemp1+alutemp2; //out=in1+in2;
   $display("in1 %x and in2 %x and out %x\n",in1,in2,out);
 end
end 

Please advice, Thanks

Answer 1

我认为您的加法器不能正常工作（因为它不能在我正在使用的软件中编译）。但是，如果您将代码更改为以下内容：

module Verilog1(out, in1, in2, sub);
output reg[31:0] out;
input [31:0] in1, in2;
input [4:0] sub;

always @(*) 
  begin
    out <= in1 + in2;
    $display("in1 %x and in2 %x and out %x\n",in1,in2,out);
  end 
endmodule

对于输入in1 = 0，in2 = -1您会得到0xffff_ffff.