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我正在使用 VHDL 和 Nexys 2 FPGA 在 Xilinx webpack 中工作，并试图习惯于制作模块化代码。所以我的项目包含3个短文件：main.vhd、Adder_4bit.vhd和constraints.ucf。我的代码编译良好，但 LED 6 亮起，并且没有任何响应对开关的任何更改做出应有的反应。这是我的文件：

主要的.vhd

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( switches : in  STD_LOGIC_VECTOR (7 downto 0);
           LEDs : out  STD_LOGIC_VECTOR (7 downto 0));
end main;

architecture Behavioral of main is
COMPONENT Adder_4bit
PORT(
    x : IN std_logic_vector(3 downto 0);
    y : IN std_logic_vector(3 downto 0);
    cin : IN std_logic;          
    cout : OUT std_logic;
    sum : OUT std_logic_vector(3 downto 0);
    gp : OUT std_logic;
    gg : OUT std_logic
    );
END COMPONENT;

signal zero : STD_LOGIC;

begin

Inst_Adder_4bit: Adder_4bit PORT MAP(
        x => switches(7 downto 4),
        y => switches(3 downto 0),
        cin => zero,
        cout => LEDs(7),
        sum => LEDs(3 downto 0),
        gp => LEDs(6),
        gg => LEDs(5)
    );
LEDs(4) <= '0';
end Behavioral;

Adder_4bit.vhd

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Adder_4bit is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
           sum : out  STD_LOGIC_VECTOR (3 downto 0);
              gp : out STD_LOGIC;
              gg : out STD_LOGIC);
end Adder_4bit;

architecture Behavioral of Adder_4bit is
    signal p        : STD_LOGIC_VECTOR (3 downto 0);
    signal g        : STD_LOGIC_VECTOR (3 downto 0);
    signal iCarry : STD_LOGIC_VECTOR (4 downto 0);

begin
    p <= x or y;
    g <= x and y;
    iCarry(0) <= cin;
    iCarry(1) <= g(0) or (p(0) and iCarry(0));
    iCarry(2) <= g(1) or (p(1) and iCarry(1));
    iCarry(3) <= g(2) or (p(2) and iCarry(2));
    iCarry(4) <= g(3) or (p(3) and iCarry(3));
    sum(0) <= x(0) xor y(0) xor iCarry(0);
    sum(1) <= x(1) xor y(1) xor iCarry(1);
    sum(2) <= x(2) xor y(2) xor iCarry(2);
    sum(3) <= x(3) xor y(3) xor iCarry(3);
    cout <= iCarry(4);
    gp <= p(0) and p(1) and p(2) and p(3);
    gg <= g(3) or (g(2) and p(3)) or (g(1) and p(2) and p(3)) or (g(0) and p(1) and p(2) and p(3));

end Behavioral;

最后是constraints.ucf

NET switches(7) LOC = "R17";
NET switches(6) LOC = "N17";
NET switches(5) LOC = "L13";
NET switches(4) LOC = "L14";
NET switches(3) LOC = "K17";
NET switches(2) LOC = "K18";
NET switches(1) LOC = "H18";
NET switches(0) LOC = "G18";

NET LEDs(7) LOC = "R4";
NET LEDs(6) LOC = "F4";
NET LEDs(5) LOC = "P15";
NET LEDs(4) LOC = "E17";
NET LEDs(3) LOC = "K14";
NET LEDs(2) LOC = "K15";
NET LEDs(1) LOC = "J15";
NET LEDs(0) LOC = "J14";

#NET LCD_a0 LOC = "F17";
#NET LCD_a1 LOC = "H17";
#NET LCD_a2 LOC = "C18";
#NET LCD_a3 LOC = "F15";

#NET LCD_A LOC = "L18";
#NET LCD_B LOC = "F18";
#NET LCD_C LOC = "D17";
#NET LCD_D LOC = "D16";
#NET LCD_E LOC = "G14";
#NET LCD_F LOC = "J17";
#NET LCD_G LOC = "H14";
#NET LCD_DP LOC = "C17";

#NET clock LOC = "B8";
#NET "clock" TNM_NET = clock;
#TIMESPEC TS_clk = PERIOD "clock" 4 ns HIGH 50%;

提前致谢。

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2 回答 2

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我现在无法使用合成器，但我认为问题在于您尚未初始化零值。

当未定义信号时，您的优化器可能会优化您不想要的东西。

尝试将零信号声明为常数或将 cin 连接到“0”。

（我本来只想发表评论，但似乎您需要更多代表才能做到这一点）

于 2013-07-16T08:25:03.470 回答
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我找到了我的问题的答案。事实证明，赛灵思 ISE 生成了两个位文件，每个 VHD 文件一个。所以我的项目文件夹中有一个 Adder_4bit.bit 和一个 main.bit 文件。在我的代码中，Adder_4bit 是在 main 中实例化的，因此我需要将 main.bit 上传到我的 FPGA 中，但是我上传了 Adder_4bit.bit 文件，这个文件对我来说很有意义，因为我的项目也称为 Adder_4bit。

简而言之，请确保您上传主位文件而不是组件位文件。

于 2013-11-19T21:00:27.760 回答