verilog - 使用时钟边沿触发的动作定时

Question

假设我有如下代码：

always @(clock)
begin
  if (condition is met)
     a <= 0
  else if (another condition is met)
     b <= 0
end

我想要一个 <= 0 在时钟的 posedge 和 b <= 0 在时钟的 negedge。我该如何指定？

我现在正在做的是...

always @(clock)
begin
   if (condition is met)
      @(posedge clock) a <= 0
   else if (another condition is met)
      @(negedge clock) b <= 0
end

Answer 1

使用两个always块。一为posedge，一为negedge。

always @(posedge clock) begin
  if (condition is met)
     a <= 0;
end
always @(negedge clock) begin
  if (!(condition is met) && (another condition is met))
     b <= 0;
end