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我被要求回答这些关于操作系统上下文切换的问题，这个问题非常棘手，我在教科书中找不到任何答案：

  1. 在特定时间，系统中存在多少 PCB？
  2. 哪两种情况会导致上下文切换发生？（我认为它们是进程的中断和终止，但我不确定）
  3. 硬件支持可以改变切换所需的时间。两种不同的方法是什么？
  4. 操作系统的哪一部分参与管理上下文切换？
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3 回答 3

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  1. 在给定时刻，系统中可以有任意数量的 PCB。每个 PCB 都链接到一个过程。
  2. 抢占式内核中的定时器中断或协作内核中放弃对处理器的控制的进程。当然，还有 I/O 操作中的进程终止和阻塞。
  3. 我不知道这里的答案，但请参阅Marko 的答案
  4. 来自内核的调度程序之一。

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于 2013-06-21T06:05:11.030 回答
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3: A whole number of possible hardware optimisations

  • Small register sets (therefore less to save and restore on context switch)
  • 'Dirty' flags for floating point/vector processor register set - allows the kernel to avoid saving the context if nothing has happened to it since it was switched in. FP/VP contexts are usually very large and a great many threads never use them. Some RTOSs provide an API to tell the kernel that a thread never uses FP/VP at all eliminating even more context restores and some saves - particularly when a thread handling an ISR pre-empts another, and then quickly completes, with the kernel immediately rescheduling the original thread.
  • Shadow register banks: Seen on small embedded CPUs with on-board singe-cycle SRAM. CPU registers are memory backed. As a result, switching bank is merely a case of switching base-address of the registers. This is usually achieved in a few instructions and is very cheap. Usually the number of context is severely limited in these systems.
  • Shadow interrupt registers: Shadow register banks for use in ISRs. An example is all ARM CPUs that have a shadow bank of about 6 or 7 registers for its fast interrupt handler and a slightly fewer shadowed for the regular one. Whilst not strictly a performance increase for context switching, this can help ith the cost of context switching on the back of an ISR.
  • Physically rather than virtually mapped caches. A virtually mapped cache has to be flushed on context switch if the MMU is changed - which it will be in any multi-process environment with memory protection. However, a physically mapped cache means that virtual-physical address translation is a critical-path activity on load and store operations, and a lot of gates are expended on caching to improve performance. Virtually mapped caches were therefore a design choice on some CPUs designed for embedded systems.
于 2013-06-21T08:42:08.260 回答
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调度器是操作系统中管理上下文切换的部分，它在以下条件之一执行上下文切换：
1.多任务

2.中断处理

3.用户和内核模式切换

每道工序都有自己的PCB

于 2013-06-21T06:06:01.460 回答