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我的问题是我读取了 ADI_DEV_CORE_STATUS 的值，它仍然为 0x2A，即使在我在位 22 上写入断言 1 以启用电源模式请求之后，我在值没有改变后直接打印出该值。

我正在尝试发送一个进入休眠模式的请求，

在 ADI DEV CORE STATUS 寄存器中，

第 26 位定义为电源模式失败（只读），

第 25 位定义为处于睡眠状态的核心（只读），

第 24 位定义为部分休眠（读/写）的电源模式请求，

第 23 位定义为休眠模式（读/写）的电源模式请求，

第 22 位定义为启用主机发起的电源模式请求（读/写），

第 21 位定义为启动发送 COMWAKE Burst 模式以从休眠中唤醒（读/写）

第 5 位被定义为 Phy-Ready（只读），

位 4 定义为复位（读/写），

第 3 位定义为指示设备状态机处于空闲状态（只读），

bits[2:0] 定义为当前接口速度（0h：无连接）（1h：已建立 Gen1 速率）（2：h：已建立 Gen 2 速率）（3h：已建立 Gen3 速率）（为后代保留的其他值）

代码中定义的其他值

u32 read;
u32 write;
u32 mask;
u32 rc;
/*Device Application Status (DevCoreStatus Register 0x002C)*/
DEV_STATUS_SIM        = (1 << 31), /*Core in Simulation*/
DEV_STATUS_PM_FAIL    = (1 << 26), /*Power Mode Fail*/
DEV_STATUS_CORE_SLEEP = (1 << 25), /*Successful Transition into Sleep Mode*/
DEV_STATUS_PARTIAL_GO = (1 << 24), /*Power Mode Request for Partial Mode*/
DEV_STATUS_SLUMBER_GO = (1 << 23), /*Power Mode Request for Slumber Mode*/
DEV_STATUS_EN_PWDN    = (1 << 22), /*Enables Host Initiated Power Mode Requests*/
DEV_STATUS_COMWAKE    = (1 << 21), /*Initiates the Sending of COMWAKE Burst Pattern to Allow for Waking up from Slumber*/
DEV_STATUS_PHYRDY     = (1 << 5), /*Indicates the Device Core has Achieved a Phy-Ready State*/
DEV_STATUS_RESET      = (1 << 4), /*Upon Exit From Reset, Device will Send a COMINIT*/
DEV_STATUS_DEVIDL     = (1 << 3), /*Device State Machine is in Idle*/
DEV_STATUS_SPEED_0    = (0x0 << 0), /*0h: No Connection to the Host Established*/
DEV_STATUS_SPEED_1    = (0x1 << 0), /*1h: Gen 1 Communication Established*/
DEV_STATUS_SPEED_2    = (0x2 << 0), /*2h: Gen 2 Communication Established*/
DEV_STATUS_SPEED_3    = (0x3 << 0), /*3h: Gen 3 Communication Established*/

struct DevDesc {
  u32 * mmio; //memory mapped io address
  u32 qd_cmd; //queued command - doesnt appear to be used yet. guessing active-high 32 bits
  u8 phy_rdy; //phy_rdy flag - set by software
  u8 spd_allowed; //same as below. doesnt appear to be used yet
  u8 cur_lnk_spd; /* 00 -> Not phyrdy, 01 -> Gen1 -> 02 -> Gen2, 03-> Gen3*/
  u8 dev_mode; /* DEV_MODE_xxx, eg SATA, SAS, dual */
  struct ata_port_operations *ops; //what is this? doesnt appear to be used
};

struct MemDesc {
  u32 * non_qd_dev_mem_addr;
  u32 non_qd_dev_mem_span;
  u32 * qd_dev_mem_addr;
  u32 qd_dev_mem_span;
  u32 * sg_addr;
  u32 sg_span;
};

struct MemDesc mem_desc_g = {
  .non_qd_dev_mem_addr = (u32*)(DEV_PORT_MEMORY_BASE), //Non-queued command memory. base=0x40000
  .non_qd_dev_mem_span = DEV_PORT_MEMORY_SPAN, //65536 bytes - 0x40000:0x4FFFF
  .qd_dev_mem_addr = (u32*)(DATA_BUFFER_BASE_ADDRESS), //Queued command buffer. base=0x50000.
  .qd_dev_mem_span = DATA_BUFFER_SPAN, //65536 bytes - 0x50000:0x5FFFF
  .sg_addr = (u32*)(DEV_SG_MEMORY_BASE), //Scatter-gather list. base=0x60000
  .sg_span = DEV_SG_MEMORY_SPAN, //65536 bytes - 0x60000:0x6FFFF
};

//System descriptor
//Points to components
struct SysDesc sys_desc_g = {
  .dd = &dev_desc, //device core descriptor
  .md = &mem_desc_g, //memory structure descriptor
};

u32 RegRead32(u32* BaseAddr, u32 Offset)
{
  u32 temp;
  temp = (u32)BaseAddr + Offset;
  return *(volatile int *)temp;
}

void RegWrite32(u32* BaseAddr, u32 Offset, u32 WriteData)
{
  u32 temp;
  temp = (u32)BaseAddr + Offset;
  *(volatile int *)temp = WriteData;
  return;
}

u32 wait_reg( u32* reg_addr, u32 mask, u32 val, u32 interval_usec, u32 timeout_usec)
{
  u32 ii = 0;
  u32 rc = 0;
  for(ii=0;ii<(timeout_usec/interval_usec); ii++){
  rc = RegRead32(reg_addr, 0);
  if((rc & mask) != val){
    return rc;
}
  //branch slot pad...
  RegRead32(reg_addr, 0);
  usleep(interval_usec);
}
//iprop_printf("%s:: wait reg timout. ending register value == %08X\n\r",__func__,rc);
return rc;
}


u32 power_mode_sleep (struct SysDesc * sd)
{
  rc = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
  alt_printf("The value of ADI_DEV_CORE_STATUS is 1.) %x \n", rc); /*Should print out 0x2A, phy-ready, in idle, and Gen2 speed*/
  rc = rc & 0xFF3FFFFF;
  rc |= DEV_STATUS_EN_PWDN; //DEV_STATUS_EN_PWDN = (1<<22)
  RegWrite32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS, rc);
  read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
  alt_printf("The value of ADI_DEV_CORE_STATUS is 2.) %x \n", read);
  rc |= DEV_STATUS_SLUMBER_GO;
  RegWrite32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS, rc);
  read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
  alt_printf("The value of ADI_DEV_CORE_STATUS is 3.) %x \n", read);
  rc = wait_reg((u32*)(DEV_BUS_SLAVE_BASE + ADI_OFFSET + ADI_DEV_CORE_STATUS),
    0x2000000, // only look at bit 25.
    0x000000, // if bit-25 == 1, We're core in sleep
    1, // wait 1us between register reads
    100000); // ~100ms
  alt_printf("The value of ADI_DEV_CORE_STATUS is 4.) %x \n", rc); /**/
  read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
  alt_printf("The value of ADI_DEV_CORE_STATUS is 5.) %x \n", read);

  if ((read & 0x2000000) == DEV_STATUS_CORE_SLEEP)
  {
    alt_printf("Successfully Transitioned into sleep mode.\n");
  }
  else if ((read & 0x4000000) == DEV_STATUS_PM_FAIL)
  {
    alt_printf("Unsuccessful Transition into sleep mode.\n");
  }
  else
    alt_printf("The value of ADI_DEV_CORE_STATUS is 6.) %x \n", rc);
    return STATUS_SUCCESS;
  }
}

我所有的 alt_printf（值是 %x”，读取）；打印出 0x2a，我应该在启用电源模式时读取 0x40002a，在启用电源模式时读取 0xC0002a，并且我正在发送休眠模式的电源请求和 0x2000000当核心处于睡眠状态时。

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1 回答 1

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首先，重写搞砸的指针算法。我假设偏移量是字节而不是 u32 字。

u32 RegRead32(u32* BaseAddr, u32 Offset)
{
  volatile u32 *temp = (volatile u32 *) ((char *) BaseAddr + Offset);
  return *temp;
}

void RegWrite32(u32* BaseAddr, u32 Offset, u32 WriteData)
{
  volatile u32 *temp = (volatile u32 *) ((char *) BaseAddr + Offset);
  *temp = WriteData;
  /* empty return at the end of a void function not needed */
}

由于您已经#定义了一些常量，因此之后不要使用它们的数值，因为您可能会犯错误。即简单测试

if (read & DEV_STATUS_CORE_SLEEP)

当该位被设置时，结果将为真。

但最重要的是，发布一个完整的代码示例（您的代码缺少一些变量声明和 wait_reg()）并尽可能简化您的测试用例。还要发布预期的输出。您写入寄存器并多次读取它们，尚不清楚哪个写入失败。

现在，如果仍然没有写入，请重新阅读数据表以确保您遵循设备期望的协议。还要寻找与该设备相关的技术说明——有时硬件有问题并且不能根据数据表运行（我过去曾在 ADI DSP 上遇到过这个问题）。如果是这样，这将是一个硬件问题，而不是一个 SO 问题。

于 2013-06-18T21:42:43.647 回答