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I'm in work placement and I have this subject in VHDL : Measurement system of response time of computer monitor. To succeed I thought about to put a photodiode in front of the monitor and switch in black and white every second the monitor to known the response time. But I don't know really how to make that, I use a spartan 3 connected at the monitor by VGA. I right a program I'm not sure if it's right, (I think it's wrong). I show you my program :

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.NUMERIC_STD.ALL

ENTITY Counter IS
        PORT(clk, rst : IN STD_LOGIC;
             sync, PhD : IN STD_LOGIC;
             s        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY Counter;

ARCHITECTURE Main OF Counter IS
SIGNAL q : UNSIGNED (3 DOWNTO 0);
BEGIN
    s <= STD_LOGIC_VECTOR(q);
    PROCESS (clk, rst) IS
        BEGIN
            IF rst='1' THEN
               q<=(OTHERS => '0');
            ELSIF RISING_EDGE(clk) THEN
                IF sync='0' THEN
                    q=q;
                ELSIF sync='1' THEN
                    IF PhD='0' THEN
                    q<=q+1;
                    ELSIF PhD='1' THEN
                    q=q;
                    END IF;
                END IF;
            END IF;
    END PROCESS;
END ARCHITECTURE Mai

n;

Tell me if you need something more maybe I forgot something. And tell me what you thing about my program.

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1 回答 1

0

你写的是一个计数器，它在每个时钟周期递增，同步为 1，phd 为 0。在不知道你的确切要求的情况下，很难说这是否是你想要的。

如果要确定sync 变为高电平和phd 变为高电平之间的时间量，则应在sync=0 时将q 设置为0。这将导致计数器在每次同步变高时从 0 开始。

您可能还应该增加 q 的宽度，具体取决于您的时钟速度。目前它只有 4 位，这意味着它将每 16 个周期回绕回 0。给定典型的时钟频率（例如 100 MHz），这不到一微秒。要以 100 MHz 计数一秒钟，您需要一个至少 27 位的计数器。

于 2013-06-18T11:30:42.150 回答