variables - Is it possible to declare variables in VHDL with an asterisk?

Question

Quite new to VHDL here, so I'm not entirely sure if this is feasible at all, but here goes:

In my test code for some RAM, I have 2 8-bit std_logic_vector variables wdata_a_v and wdata_b_v. This is all I need for the current setup, but if the ratio of read to write data length changes, I will need more variables of the name wdata_*_v. I'm trying to write the code generically so that it will function for any amount of these variables, but I don't want to declare 26 of them in the code when I will likely only need a few.

It would be nice if there was a way to declare a variable like so:

variable wdata_*_v : std_logic_vector (7 downto 0);

that would, behind the scenes, declare all of the variables that fit this framework so that I could write a loop without worrying about running out of variables.

If there's a way to write a function or procedure etc. to make this work, that would be excellent.

Answer 1

是的，您可以使用二维数组，配方：

entity TestHelper is
  generic (n: natural range 2 to 255 := 8);
end TestHelper;

architecture behavioral of TestHelper is
  type array2d is array (n-1 downto 0) of std_logic_vector(7 downto 0);
begin
   process
     variable a : array2d;
   begin
       a(0)(0) := '0';
   end process;
end architecture behavioral;

编辑：现在使用它并为每个创建类似的代码wdata_*_v：

process
   variable wdata_v : array2d;
begin
   someLabel: for i in 0 to n-1 generate
       wdata_v(i)(0) := '0';
       x <= y and z;
       ...
   end generate;

   x <= '1';
   ...

   anotherLabel: for i in 1 to n generate
      ...
   end generate;

   ...
end process;