vhdl - 我正在编写代码以在 VHDL 中生成 PWM 波，但我收到 pwmout 节点的错误同步描述错误

Question

假设 gclk 的完整 0 到 15 计数是输出 pwm 波的一个周期，pwmin 反映了占空比。当计数从 15+1 减少到 0 时，bufferreg 值首先在 gclk 的上升沿获取 pwmin 值，并且在每个连续的时钟沿检查 countreg 值并根据该值给出 pwmout

entity pwm is
port(gclk: in std_logic;
reset: in std_logic;
pwmin: in std_logic_vector(3 downto 0); --input reg to reflect the duty cycle
pwmout: out std_logic );
end pwm;

architecture Behavioral of pwm is
signal bufferreg,countreg: unsigned(3 downto 0);

signal count: integer:=16; -- count value for the one full cycle of PWM
begin
    process(gclk, reset, pwmin)
    begin
    case reset is --asynchronous reset 
    when '0' =>
            loop1: for count in 16 downto 0 loop --count is 15+1
                        if (rising_edge(gclk)) then --the buffer reg is loaded athe first clock edge
                                if (count=16) then
                                bufferreg<=unsigned(pwmin);
                                countreg<="0000";
                                else 
                                            if (countreg<=bufferreg) then
                                                        pwmout<='1'; --output high for on period
                                            elsif (countreg>bufferreg) then
                                                        pwmout<='0'; --output low for off period
                                            end if;
                                         countreg<=countreg+1 --updating of countreg
                                end if;
                         end if;
                     --next;
            end loop loop1;
    when others => 

    end case;   

end process;


end Behavioral;

Answer 1

你应该写你的代码有点像下面：

process(gclk, reset)
begin
    if reset='1' then -- asynchronous reset, high active
       ...
    elsif rising_edge(gclk) then -- synchronous stuff on rising edge
        loop1: for count...
            ...

请注意，您的“for count in 16 downto 0 loop”会导致 17 个步骤！