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使用 EDK 创建 Microbalze 在同一目录的数据文件夹中创建一个 ucf 文件，在使用以太网在 spartan 6 上创建一个简单的 microblaze 之后，我打开了 ddr3 IPS 文件：

#  Spartan-6 SP605 Evaluation Platform
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<0> LOC=C18  |  IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<1> LOC=Y6  |  IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<2> LOC=W6  |  IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<3> LOC=E4  |  IOSTANDARD=LVCMOS15;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=L20  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=P20  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=N15  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=T22  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=P19  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=Y22  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=Y21  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=W22  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=M16  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U20  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J22  |  IOSTANDARD = LVCMOS25  |  TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=T8  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=U10  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T10  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AB8  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AA8  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDC_pin LOC=R19  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDIO_pin LOC=V20  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_MDINT_pin LOC=J20  |  IOSTANDARD = LVCMOS25  |  TIG;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_we_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cke_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<13> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<14> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<15> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ldm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_odt_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_rzq_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_zio_pin IOSTANDARD = SSTL15_II;
Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Net fpga_0_clk_1_sys_clk_p_pin LOC = K21  |  IOSTANDARD=LVDS_25  |  DIFF_TERM = TRUE;
Net fpga_0_clk_1_sys_clk_n_pin LOC = K22  |  IOSTANDARD=LVDS_25  |  DIFF_TERM = TRUE;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = H8  |  IOSTANDARD=LVCMOS15  |  PULLUP  |  TIG;

如您所见，比特流已生成，在 fpga 上编程，并且所有示例在使用 sdk 编译并在硬件上启动时都可以正常工作，但是当 DDR3 的位置不在 ucf 文件中时，一切如何正常工作？

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2 回答 2

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我不具体了解 microblaze/edk 设置，但我知道当我将 coregen 用于其他组件（dcms）等时，会为这些组件创建其他 ucf 文件。例如，如果我转到 project_dir/ipcore_dir/，我会为我创建的每个 coregen 模块看到一个单独的 ucf 文件。您的项目目录中可能还有其他一些您没有看到的定义文件（因为基于您的其他帖子，我假设您正在使用评估工具包）。如果您深入研究目录结构，您可能会找到它。如果您很好奇，请尝试搜索您在 ucf 文件中看到的 DDR3 网络名称。我敢打赌，您会找到另一个包含他们在船上的引脚位置的 ucf。

于 2013-06-10T19:26:36.457 回答
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Spartan-6 使用硬连线核心模块作为 DDR 接口。我没有经历过 S6 流程，但由于您无法选择引脚位置，因此它们根本不是 UCF 选项，我并不感到惊讶。

不同的 DDR 存储器具有不同的电源电压，因此在此处指定 IOSTANDARD 确实有意义。

于 2013-06-10T21:06:26.630 回答