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这是我正在使用的代码,但我需要放慢时钟以查看列和行的变化情况。我认为我的时钟存在一些问题:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dot_matrix is

  port (main_clk, en : in std_logic;


        switches : in    std_logic_vector (3 downto 0);
        rows     : inout std_logic_vector (6 downto 0);
        col      : inout std_logic_vector (4 downto 0));

end dot_matrix;

architecture Behavioral of dot_matrix is

  signal row_count  : std_logic_vector(2 downto 0);
  signal counter    : integer range 0 to 25000000 := 0;  -- to divide the clock down
  signal slow_clock : std_logic                   := '0';

begin

  clockdiv1 : process(main_clk)
  begin
    if main_clk'event and main_clk = '1' then
      if counter = 24999999 then
        counter    <= 0;
        slow_clock <= not slow_clock;
      else
        counter <= counter + 1;
      end if;
    end if;
  end process clockdiv1;

  SM : process (slow_clock)
  begin
    if (slow_clock'event and slow_clock = '1') then
      if (en = '1') then
        if (row_count = "100") then
          row_count <= "000";
        else
          row_count <= row_count + 1;
        end if;
      else
        row_count <= "000";
      end if;
    end if;
  end process SM;



  DIS : process (row_count)
  begin

    if row_count = "000" then           --1st clock count
      col  <= "01111";                  --selecting 1st column
      rows <= "1111111";                -- putting the data on the 1st column

    elsif row_count = "001" then        -- 2nd clock count
      col  <= "10111";                  -- selecting 2nd column
      rows <= "1001000";

      row_count = "010" then            -- 3rd clock count
        col  <= "11011";                -- selecting 3rd column 
        rows <= "1001100";

      elsif row_count = "011" then      -- 4th clock count
        col  <= "11101";                -- selecting 4th column 
        rows <= "1001010";

      elsif row_count = "100" then      -- 5th clock count
        col  <= "11110";                -- selecting 5th column 
        rows <= "0110001";

        -- 1 1 1 1 0

        -- 1 0 0 0 1

        -- 1 0 0 0 1

        -- 1 1 1 1 0

        -- 1 0 1 0 0

        -- 1 0 0 1 0

        -- 1 0 0 0 1

      end if;
  end process DIS;

end Behavioral;

编辑:修复代码缩进后需要添加一些文本。

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2 回答 2

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您正在为慢速时钟使用初始值'0'。您需要验证您的合成器和目标技术是否支持这一点。有些FPGA可以,有些不。或者,您可以添加一个复位信号并在启用复位时设置一个值。

其他的建议:

于 2013-06-06T12:31:00.857 回答
0

行中缺少“elsif”

row_count = "010" then

也许这已经解决了您的问题。

于 2013-06-06T11:05:06.907 回答