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I read the Datasheet for an Intel Xeon Processor and saw the following:

The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels with 8 bits of ECC for each channel (total of 72-bits) and supports 1 to 3 DIMMs per channel depending on the type of memory installed.

I need to know what this exactly means from a programmers view.
The documentation on this seems to be rather sparse and I don't have someone from Intel at hand to ask ;)

  1. Can this memory controller execute 4 loads of data simultaneously from non-adjacent memory regions (and request each data from up to 3 memory DIMMs)? I.e. 4x64 Bits, striped from up to 3 DIMMs, e.g:
    | X | _ | X | _ | X | _ | X |
    (X is loaded data, _ an arbitrarily large region of unloaded data)

  2. Can this IMC execute 1 load which will load up to 1x256 Bits from a contiguous memory region.
    | X | X | X | X | _ | _ | _ | _ |

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这似乎是特定于实现的，取决于编译器、操作系统和内存控制器。该标准可在以下网址获得：http: //www.jedec.org/standards-documents/docs/jesd-79-3d。似乎如果您的控制器完全兼容，则可以设置特定位以指示交错或非交错模式。请参阅 DDR3 规范的第 24,25 和 143 页，但即使在规范中的细节也很简单。

特别是对于 i7/i5/i3 系列，可能是所有较新的英特尔芯片，内存是交错的，就像你的第一个例子一样。对于这些较新的芯片和可能支持它的编译器，是的，一个 Asm/C/C++ 级别的调用来加载足够大的东西以进行交错/条带化将启动所需数量的独立硬件通道级别加载到每个内存通道。

在维基百科多通道内存页面的三通道部分中，有一小部分 CPU 执行此操作，可能不完整：http ://en.wikipedia.org/wiki/Multi-channel_memory_architecture

于 2013-05-28T14:48:11.883 回答