为什么信号“state”和“return_state”的值不会在modelsim波形中切换。我正在使用（ISE Design Suite 14.1）测试平台和 ModelSim SE plus 6.5 模拟 SD 接口（SPI 总线）。问题是 FSM 中的状态名称不会在波形中切换。信号“state”和“return_state”始终处于“RST”状态。我已经在测试台中声明了信号“状态”、“返回状态”和“类型状态”。当我通过步进函数进行模拟时，指针显示模拟在状态之间切换。当状态发生变化时，我需要查看波形，但我不知道我做错了什么。代码在http://stevenmerrifield.com/tools/sd.vhd上。请帮忙。
clk_period = 20 ns
代码的初始部分：
begin
process(clk,reset)
variable byte_counter : integer range 0 to WRITE_DATA_SIZE;
variable bit_counter : integer range 0 to 160;
begin
data_mode <= dm_in;
if rising_edge(clk) then
if (reset='1') then
state <= RST;
sclk_sig <= '0';
else
case state is
when RST =>
sclk_sig <= '0';
cmd_out <= (others => '1');
address <= x"00000000";
byte_counter := 0;
cmd_mode <= '1'; -- 0=data, 1=command
response_mode <= '1'; -- 0=data, 1=command
bit_counter := 160;
cs <= '1';
state <= INIT;
when INIT => -- CS=1, send 80 clocks, CS=0
if (bit_counter = 0) then
cs <= '0';
state <= CMD0;
else
bit_counter := bit_counter - 1;
sclk_sig <= not sclk_sig;
end if;
when CMD0 =>
cmd_out <= x"FF400000000095";
bit_counter := 55;
return_state <= CMD55;
state <= SEND_CMD;
如果“reset”信号设置为“1”，然后返回“0”，则“rst”状态的信号除了“cs”和“mosi”设置为“1”外不会改变。“state”应该得到值“INIT”，80个时钟后得到值“CMD0”，但它保持值“rst”。然后：
-在 3310 ns "cs" 获取值 '0'
什么时候应该发生的代码部分：
when INIT => -- CS=1, send 80 clocks, CS=0
if (bit_counter = 0) then
cs <= '0';
state <= CMD0;
似乎“状态”具有或应该具有值“INIT”，但在波形中它仍然具有值“rst”。
试验台：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY simulacija IS
END simulacija;
ARCHITECTURE behavior OF simulacija IS
COMPONENT sd_controller
PORT(
cs : OUT std_logic;
mosi : OUT std_logic;
miso : IN std_logic;
sclk : OUT std_logic;
rd : IN std_logic;
wr : IN std_logic;
dm_in : IN std_logic;
reset : IN std_logic;
din : IN std_logic_vector(7 downto 0);
dout : OUT std_logic_vector(7 downto 0);
clk : IN std_logic
);
END COMPONENT;
signal miso : std_logic := '0';
signal rd : std_logic := '0';
signal wr : std_logic := '0';
signal dm_in : std_logic := '0';
signal reset : std_logic := '0';
signal din : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal cs : std_logic := '0';
signal mosi : std_logic;
signal sclk : std_logic;
signal dout : std_logic_vector(7 downto 0);
type states is (
RST,
INIT,
CMD0,
CMD55,
CMD41,
IDLE,
READ_BLOCK,
READ_BLOCK_WAIT,
READ_BLOCK_DATA,
READ_BLOCK_CRC,
SEND_CMD,
RECEIVE_BYTE_WAIT,
RECEIVE_BYTE,
WRITE_BLOCK_CMD,
WRITE_BLOCK_INIT,
WRITE_BLOCK_DATA,
WRITE_BLOCK_BYTE,
WRITE_BLOCK_WAIT
);
signal state, return_state : states;
signal sclk_sig : std_logic := '0';
signal cmd_out : std_logic_vector(55 downto 0);
signal recv_data : std_logic_vector(7 downto 0);
signal address : std_logic_vector(31 downto 0);
signal cmd_mode : std_logic := '0';
signal data_mode : std_logic := '1';
signal response_mode : std_logic := '0';
signal data_sig : std_logic_vector(7 downto 0) := x"00";
constant clk_period : time := 20 ns;
BEGIN
uut: sd_controller PORT MAP (
cs => cs,
mosi => mosi,
miso => miso,
sclk => sclk,
rd => rd,
wr => wr,
dm_in => dm_in,
reset => reset,
din => din,
dout => dout,
clk => clk
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
reset <= '1';
wait for 80 ns;
reset <= '0';
wait;
end process;
END;