vhdl - 这个设计有什么问题

Question

我有一些 VHDL 代码在合成时表现得很奇怪，但我怀疑这是我对 VHDL 合成的基本理解是错误的。

“同步”是一个短脉冲（大约半个 clk 周期），它在 clk 上升沿为高电平，但不久后变为低电平。在综合期间，当同步为高时，在 clk 上升沿上仅分配一些信号分配。

同步是否需要在最短的时间内保持较高水平？

process(clk)
begin
if rising_edge(clk) then
   if sync = '1' then
      a <= '1';
      y3 <= y2;
      y2 <= y1;
      y1 <= y0; 
   end if;
end if;
...

只有“a”在合成时更新其值....

Answer 1

I can only guess since you don't show the whole of the process.

Signal do not get updated until after a process is run. So if you are using signals as intermediate variables other signals won't be updated as you expect.

if a is a signal which has value 1 before the process.
process(clk)
     ...
     a <= '0'
     a still has value 1 here
     ....
end process
a's value is now updated to 0