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我们正在为我的大学项目设计一个机器人，我们是电气工程专业的一年级学生。机器人必须使用简单的 LC 振荡器和比较器来检测地雷。这个电路的输出是一个块波，这样我们的FPGA就可以计数到指定的数字，然后和一个预先定义的数字比较，看看振荡器的频率有没有变化（意思是有金属物体在传感器下）。我写了这个，但似乎rising_edge（传感器）不起作用，不明白，因为两个计数器实际上是相同的。时钟的实体是完全一样的，但是以时钟为输入。

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;

entity metaal_detector is
  port(
    sensor, reset: in std_logic;
    sensor_out: out std_logic_vector(10 downto 0)
 );
 end entity metaal_detector;

 architecture behavioural of metaal_detector is
signal  count, new_count    : unsigned (10 downto 0);

begin
process (sensor)
begin
    if (rising_edge (sensor)) then
        if (reset = '1') then
            count   <= (others => '0'); -- zet op 0 bij reset
        else
            count   <= new_count;
        end if;
    end if;
end process;

process (count)
begin
    new_count   <= count + 1;   
end process;

sensor_out  <= std_logic_vector (count);
end architecture behavioural;

这是我的测试台：

 library IEEE;
 use IEEE.std_logic_1164.all;

 entity testbench is
 end entity testbench;

 architecture test of testbench is

  component sensor_control is
    port(
    clk, reset, sensor: in std_logic;
   metaal: out std_logic;
   reset_teller: out std_logic
   );
 end component;

  component counter is
   port(
   clk, reset: in std_logic;
   count_out: out std_logic_vector(10 downto 0)
   );
 end component;

 component metaal_detector is
  port(
 sensor, reset: in std_logic;
 sensor_out: out std_logic_vector(10 downto 0)
 );
 end component;

  signal sensor, clock, reset, metaal, reset_teller: std_logic; 
   signal count1, sensor1: std_logic_vector(10 downto 0);

   begin

  clock <=       '1' after  0 ns,
             '0' after 10 ns when clock /= '0' else '1' after 10 ns;
    reset   <=       '1' after 0 ns,
                     '0' after 35 ns;
    sensor   <=  '1' after  0 ns,
             '0' after 30 ns when sensor /= '0' else '1' after 30 ns;


 lblb0: sensor_control port map (clock, reset, sensor, metaal, reset_teller);                       
 lbl0: counter port map(clock, reset_teller, count1);
 lbl1: metaal_detector port map(sensor, reset_teller, sensor1);
 end architecture test;

如果我在某处使用 clk 而不是 clock 是因为如果尝试了很多事情。

感谢您能解释一下我做错了什么。

大卫·凯斯特

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1 回答 1

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您无需将“new_count”内容与“count”内容分开......只需将它们组合成一个进程！计数器（具有同步复位）通常实现如下：

process (clock) 
begin
   if rising_edge(clock) then
      if reset='1' then 
         count <= (others => '0');
      else      -- or, with clock enable:  elsif clock_enable='1' then
         count <= count + 1;
      end if;
   end if;
end process;
于 2013-05-21T06:12:28.437 回答