所以我目前正在为每秒显示一次(0-F)的 7 段显示器编写 VHDL 代码。我几乎完成了所有事情,我唯一坚持的就是控制器。
我需要 4 个按钮,第一个启动计数器,第二个停止它,第三个将其递增 1,最后一个将其重置为 0(我已经完成了最后一个,我只需要前三个)
这是我的整体代码(请注意,问题 2 组件是我的计数器):
entity SSD is
port (
seg : out std_logic_vector (6 downto 0);
an3 : out std_logic;
btn1, btn2, btn3, btn4 : in std_logic;
clk : in std_logic);
end SSD;
architecture Behavioral of SSD is
component hex7seg is
port (
x : in std_logic_vector (3 downto 0);
a_to_g : out std_logic_vector (6 downto 0));
end component;
component Problem2 is
port (
clr : in std_logic;
ce : in std_logic;
clk : in std_logic;
b : out std_logic_vector (3 downto 0);
tc : out std_logic);
end component;
component clkdiv is
port (
rst : in std_logic;
clk : in std_logic;
clkout : out std_logic);
end component;
component controller is
port (
start : in std_logic;
stop : in std_logic;
inc : in std_logic;
rst : in std_logic;
clk : in std_logic;
run : out std_logic);
end component;
signal b : std_logic_vector(3 downto 0);
signal run : std_logic;
signal clk_1sec : std_logic;
signal tc : std_logic;
begin
U1: hex7seg port map (x => b, a_to_g => seg);
U2: Problem2 port map (clr=>btn4, ce=>run, clk=>clk_1sec, b=>b, tc=>tc);
U3: controller port map (start => btn1, stop => btn2, inc => btn3, rst => btn4, clk => clk_1sec, run => run);
U4: clkdiv port map (rst => btn4, clk => clk, clkout => clk_1sec);
an3 <= '0';
end Behavioral;
这是我到目前为止的控制器代码:
entity controller is
Port ( start : in STD_LOGIC;
stop : in STD_LOGIC;
inc : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
run : out STD_LOGIC);
end controller;
architecture Behavioral of controller is
begin
run <= '1';
end Behavioral;
我不确定从那里去哪里才能让其他 3 个按钮正常工作,任何帮助或指导将不胜感激。