vhdl - 使用 VHDL 配置 RS232 到 USB 电缆

Question

我正在使用 VHDL 配置 RS232 到 USB 电缆，我似乎遇到了问题。我不知道如何配置双端口 RAM。我试图搜索答案，并找到了一些代码，但我不完全了解如何应用此代码。此代码可在此链接中找到 --> http://www.asic-world.com/examples/vhdl/ram_dp_ar_aw.html。请尽快提供帮助，我急需这些信息。

Answer 1

----------------------------------------------------------------------------------

-- Create Date   : 14:06:22 12/08/2013 
-- Designer Name : Sarin anand k
-- Module Name   : UART - Behavioral 
-- Project Name  : RS232 transmitter

----------------------------------------------------------------------------------

-- spartan 3 starter kit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;

entity uart is
port(
  sys_clk : in  std_logic;  --50Mhz
  reset   : in  std_logic;
  data_in : in  std_logic_vector(7 downto 0); -- switch
  load    : in  std_logic; --push button
  Tx      : out std_logic
    );  
end uart;

architecture Behavioral of uart is

  type T_state is (IDLE,STORAGE,START, DATA, STOP);

-- baud rate = 115200, bit duration required is 1/115200 = 8680 ns
-- for a 50MHz clock, period is 20 ns. So each bit is 8680/20 = 434 clock cycles

  constant bit_dur        : std_logic_vector(15 downto 0) := X"01B3";   -- 434 clocks
  constant start_bit      : std_logic := '0';
  constant stop_bit       : std_logic := '1';
  signal   baud_cnt       : std_logic_vector(23 downto 0) := X"000000"; -- 115200
  signal   baud_en        : std_logic;
  signal   temp           : std_logic_vector(7 downto 0);
  signal   baud_rate_cnt  : std_logic_vector(7 downto 0):=(others => '0');
  signal   bit_cnt_start  : std_logic;
  signal   baud_flag      : std_logic;
  signal   state          : T_state;

 begin
-----------------------------------------------------------------------------------------------------
---- baud clock
------------------------------------------------------------------------------------------------------

baud_rate: process(sys_clk) begin
  if rising_edge(sys_clk) then
    if (reset = '1') then
       baud_cnt <= X"000000"; 
       baud_en <= '0';
     end if;
      if  (baud_cnt = bit_dur)then
         baud_en <= '1';                        -- data in flag
         baud_cnt <= X"000000";
       elsif(bit_cnt_start = '1') then
         baud_cnt<= baud_cnt + '1';
          baud_en <= '0';
     end if;
  end if;
end process baud_rate;

---------------------------------------------------------------------------------------------------------------
-- baud clock counter
----------------------------------------------------------------------------------------------------------------

baud_counter: process(sys_clk) begin
  if(rising_edge (sys_clk)) then
    if(reset = '1') then
       baud_rate_cnt <=( others => '0');
       baud_flag <= '0';
     end if;
      if( baud_rate_cnt = "1000") then
         baud_flag <= '1';
         baud_rate_cnt <=( others => '0');
       elsif( state = DATA and baud_en ='1') then
         baud_rate_cnt <= baud_rate_cnt + '1';
         baud_flag <= '0';
      end if;
  end if;
end process baud_counter;


--------------------------------------------------------------------------------------------------------------------      
-- State machine to control the data flow
----------------------------------------------------------------------------------------------------------------------


control_flow: process (sys_clk) begin
  if(rising_edge (sys_clk)) then
    if (reset = '1') then
       bit_cnt_start <= '0';
       state <= IDLE;
     end if;
         case state is
         when  IDLE         =>
            state           <= STORAGE;
           when STORAGE       =>
              if  (load = '1') then
                state          <= START;
                bit_cnt_start  <= '1';
              end if; 
         when START         => 
              if  (baud_en ='1') then
              state         <= DATA;
              end if;  
            when DATA          =>
              if ((baud_en ='1') and (baud_flag = '1')) then          
             state          <= STOP;
              end if;
         when STOP           => 
           if (baud_en = '1') then
             state           <= IDLE;
                 bit_cnt_start   <= '0';
           end if;
         when others         =>
           state             <= IDLE;
        end case;
   end if;
 end process control_flow;

------------------------------------------------------------------------------------------------------------------------ 
 -- Data Transmission
-------------------------------------------------------------------------------------------------------------------------

data_trans: process (sys_clk) begin
  if (rising_edge(sys_clk)) then
    if  (reset = '1') then
      temp <= (others => '0');
     end if;
      -- Data Mux
      case state is
          when IDLE      =>
            temp         <= (others => '0'); 
          when STORAGE   =>
            temp         <= data_in; 
        when START     =>
          Tx <= start_bit;
        when DATA      =>
          Tx           <= temp(0);        
            if ( baud_en = '1') then
            temp       <=  '0' & temp(7 downto 1) ;
               Tx         <= temp(0);  
          end if;
        when STOP      =>
          Tx           <= stop_bit;
        when others    =>
          Tx           <= '1';
       end case;
     end if;
end process data_trans;

end Behavioral;