vhdl - 在 VHDL 中使用 4:1 多路复用器进行异或

Question

我需要使用 4:1 Mux 创建 XOR（我知道没有 Mux 会更容易......）

我发现这个 4:1 的有用示例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer4_1 is
port (
      i0 : in std_logic;
      i1 : in std_logic;
      i2 : in std_logic;
      i3 : in std_logic;
     sel : in std_logic_vector(1 downto 0);
     bitout : out std_logic
     );
end multiplexer4_1;

architecture Behavioral of multiplexer4_1 is
begin

process(i0,i1,i2,i3,sel)
begin
case sel is
  when "00" => bitout <= i0;
  when "01" => bitout <= i1;
  when "10" => bitout <= i2;
  when others => bitout <= i3; 
end case; 
end process;

end Behavioral;

但是我有点困惑如何告诉多路复用器在 01 或 10 是输入时输出 1，否则为 0。我可以为 i0-i3 赋值吗？抱歉，我是 VHDL 新手

Answer 1

I'm assuming you have to build an XOR gate with 2 inputs. One possibility would be to connect the two inputs to sel(0) and sel(1) respectively. You can then connect constant values to your remaining inputs i0 to i3 such that the truth table of your MUX4 is the same as for an XOR gate.

Answer 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity xor4_1 is
port (
  --i0 : in std_logic;
  --i1 : in std_logic;
  --i2 : in std_logic;
  --i3 : in std_logic;
 sel : in std_logic_vector(1 downto 0);
 bitout : out std_logic
 );
end xor4_1;

architecture Behavioral of xor4_1 is

signal    i0 : std_logic;
signal    i1 : std_logic;
signal    i2 : std_logic;
signal    i3 : std_logic;



begin

process(i0,i1,i2,i3,sel)
begin
case sel is
  when "00" => bitout <= i0;
  when "01" => bitout <= i1;
  when "10" => bitout <= i2;
  when others => bitout <= i3; 
end case; 
end process;

-- Now just hardcode the input bits to the appropriate values.
-- I might be mistaken, but I'm pretty sure this is how the implementation tool
--s actually would implement an XOR gates.
i0    <= '0';
i1    <= '1';
i2    <= '1';
i3    <= '0';

end Behavioral;

Answer 3

您的 MUX 根据选择的信号将一个输入连接到输出。

如果您想象选择信号是 XOR 门的“输入”，您只需要弄清楚 XOR 输入（选择信号）的每种组合的输出应该是什么。然后连接 MUX 输入，以便为每个选择输入输出正确的电平。

VHDL 语法只是

inst: entity work.multiplexer4_1 
port map
(
   i0 => '1'; -- or '0'

etc..

   sel => xor_input_signals;
   bitout => xor_output_signal
);