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I have the following problem: I have to implement 8 bit left shifter that makes one shift to left, the code of it is:

entity left_shift is

generic ( N: integer := 8);

Port(
    Databitsin : in STD_LOGIC_vector(N-1 downto 0);
    Databitsout : out STD_LOGIC_vector(N-1 downto 0);
    Carry: out std_logic  
);

end left_shift;

architecture Behavioral_l of left_shift is
begin
    Databitsout(N-1 downto 1)<= Databitsin(N-2 downto 0);
    Carry<=Databitsin(N-1);
end Behavioral_l;

then i have to implement another one that has to make one shift to the right

entity Right_shift is
generic ( N: integer := 8);
Port(
    Databitsin : in STD_LOGIC_vector(N-1 downto 0);
    Databitsout : out STD_LOGIC_vector(N-1 downto 0);
    Carry: out std_logic 
);

end Right_shift;

architecture Behavioral of Right_shift is
begin
    Databitsout(N-2 downto 0)<= Databitsin(N-1 downto 1);
    Carry<=Databitsin(0);
end Behavioral;

Now, I have to build a main Module which has to use these 2 components to make cyclically shift (left,right). How can I do that?

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2 回答 2

1

这听起来很像家庭作业，但绝不是这样：

首先，为什么必须使用两个组件？优雅的解决方案是编写一个能够向左或向右移动的组件。

如果您有一些非常好的理由按照您建议的方式做事，请尝试实例化两者并根据所需的指令在两者的 databitsout 信号之间进行多路复用。要进行循环移位而不是线性移位，您需要将进位位连接到逻辑向量数组的适当末端。

于 2013-04-28T21:32:05.810 回答
1

有不同的方法来实现循环移位（=旋转！）。如果添加方向选择器Dir，则可以在一个代码中同时拥有两个方向。

例 1

添加“使用 IEEE.NUMERIC_STD.all”以使用 numeric_std 包功能：

Databitsout<=std_logic_vector(rotate_right(unsigned(Databitsin),1)) when Dir='0' else
             std_logic_vector(rotate_left(unsigned(Databitsin),1));

前任。2

直接使用 std_logic_vectors ：

Databitsout<=Databitsin(0) & Databitsin(N-1 downto 1) when Dir='0' else
             Databitsin(N-2 downto 0) & Databitsin(N-1);

两者的进位标志相同：

Carry<=      Databitsin(0) when Dir='0' else 
             Databitsin(N-1);
于 2013-04-29T07:14:09.823 回答