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假设我有两个名为reg_operand1和reg_operand2的寄存器。对于他们两个，我都有一个适当的写使能信号。在我读到的某个地方，我应该为每个寄存器分配单独的过程，如下所示：

process(CLK, RESET)
begin
    if (RESET = '1') then
        reg_operand1 <= (others => '0');
    elsif (CLK'event and CLK = '1') then
        if reg_operand1_we='1' then 
            reg_operand1 <= DI;
        end if;
    end if;
end process;

process(CLK, RESET)
begin
    if (RESET = '1') then
        reg_operand2 <= (others => '0');
    elsif (CLK'event and CLK = '1') then
        if reg_operand2_we='1' then 
            reg_operand2 <= DI;
        end if;
    end if;
end process;

但是，如果我将这些流程合并到其中会发生什么？合成的电路会不一样吗？另外，如果我在合并过程中的 if 语句之间放置“elsif”怎么办？合成器会在电路中插入多路复用器吗？谢谢！

process(CLK, RESET)
begin
    if (RESET = '1') then

        reg_operand1 <= (others => '0');
        reg_operand2 <= (others => '0');

    elsif (CLK'event and CLK = '1') then

        if reg_operand1_we='1' then 
            reg_operand1 <= DI;
        end if;

        if reg_operand2_we='1' then 
            reg_operand2 <= DI;
        end if;

    end if;
end process;
4

2 回答 2

2

第二个将产生与第一个完全相同的硬件，并且如前所述，包含更少的样板。

如果我正确理解了您关于 elsif 的问题，您的提议是：

process(CLK, RESET)
begin
    if (RESET = '1') then

        reg_operand1 <= (others => '0');
        reg_operand2 <= (others => '0');

    elsif (CLK'event and CLK = '1') then

        if reg_operand1_we='1' then 
            reg_operand1 <= DI;
        elsif reg_operand2_we='1' then 
            reg_operand2 <= DI;
        end if;
    end if;
end process;

这会产生不同的硬件，也会产生不同的行为。

在没有 elsif 的示例中，当 reg_operand2_we 为高时，无论 reg_operand1_we 的状态如何，都会为 reg_operand2 分配 DI。

使用 elsif 时，reg_operand2 的赋值仅在 reg_operand2_we 为高且 reg_operand1_we 为低时发生

通常，如果两个赋值不相互依赖，请使用单独的 if 构造。

于 2013-04-28T09:22:38.053 回答
1

The second one is shorter and simpler, and will generate the same hardware. (from a brief inspection : i.e. assuming there are no accidental typos in one or the other)

An elsif in the second version, combining the two register writes, will just prioritise the registers; i.e. if you attempt to write to both registers by asserting both we signals in the same cycle, only reg_operand1 will actually be written. It will have no other effect on the design.

So...

Unless you have specific corporate style guides that prohibit it, use the second style as a general rule.

There may be a FEW cases where you want to COMPLETELY separate some functionality to make it clear that it IS separate; in that case it's better not to be dogmatic about this style; but USUALLY fewer lines of code means less to go wrong, especially where (as here) it's easier to read and understand.

"I read somewhere" ... it would be worth knowing where you read this. There are a LOT of excruciatingly bad books, teaching materials and example projects out there, waiting to ruin potential VHDL programmers, and it's worth publicising which ones to avoid...

于 2013-04-27T16:11:18.623 回答