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I have a project where i am supposed to develop a RISC microprocessor . this involves creating an ALU in behavioral model . however there seems to be problems/errors/warnings while simulating the design . most of the operations work properly except following :

COMPARING THE 2 INPUTS : when numbers are equal , zero flag is not getting set . ( unequal numbers are working properly ) .

Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

( this appears every 1 ps , presumably due to the wait statement in the process )

I Wish to work with std_logic_vector, even though i read that they are very messy .

also, there is a problem when i try to use comparing commands ( which update the flags but dont store the difference in the output register ) . How are if commands executed in VHDL ?? are they executed at the same time ?? or line by line ??

CODE BELOW :

   LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;  
USE IEEE.STD_LOGIC_ARITH.ALL;  
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 

ENTITY ALU IS
  PORT(
      INPUT1 , INPUT2: IN STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; 
      CARRYIN : IN STD_LOGIC ; 
       ZERO,CARRYOUT : OUT STD_LOGIC ; 
       OUTPUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; 
       CONTROL : IN STD_LOGIC_VECTOR(7 DOWNTO 0 )  
        ) ; 
END ALU ; 

ARCHITECTURE OPERATION OF ALU IS
SIGNAL TMP : STD_LOGIC_VECTOR( 8 DOWNTO 0 ) ; 
BEGIN
PROCESS
BEGIN
  IF( CONTROL = "00110000" OR CONTROL(7 DOWNTO 3 )  = "00001" ) THEN TMP <= CARRYIN & ( INPUT1 AND INPUT2 ) ;
  ELSIF( CONTROL(7 DOWNTO 3 ) = "00010" ) THEN TMP <= CARRYIN & ( INPUT1 OR INPUT2 ) ;
  ELSIF( CONTROL(7 DOWNTO 3 ) = "00011" ) THEN TMP <= CARRYIN & ( INPUT1 XOR INPUT2 ) ;
  ELSIF( CONTROL(7 DOWNTO 3 ) = "00100" ) THEN TMP <= CONV_STD_LOGIC_VECTOR(  ( CONV_INTEGER(INPUT1)+1 ) , 9 ) ; 
  ELSIF( CONTROL(7 DOWNTO 3 ) = "00101" ) THEN TMP <= CONV_STD_LOGIC_VECTOR(  ( CONV_INTEGER(INPUT1)-1 ) , 9 ) ; 
  ELSIF( CONTROL = "10001100" ) THEN TMP <= '0' & (NOT INPUT1) ; 
  ELSIF( CONTROL(7 DOWNTO 3 ) = "11000" OR CONTROL(7 DOWNTO 2 ) = "110010" OR CONTROL = "110-11--" ) THEN TMP <= CONV_STD_LOGIC_VECTOR(  ( CONV_INTEGER(INPUT1)+CONV_INTEGER(INPUT2) ) , 9 ) ; 
  ELSIF( CONTROL(7 DOWNTO 3 ) = "11100" OR CONTROL(7 DOWNTO 2 ) = "111010" OR CONTROL = "111-11--" OR CONTROL(7 DOWNTO 3 ) = "00000" OR CONTROL = "00111000" ) THEN TMP <= CONV_STD_LOGIC_VECTOR(  ( CONV_INTEGER(INPUT1)-CONV_INTEGER(INPUT2) ) , 9 ) ; 
  ELSIF( CONTROL(7 DOWNTO 3 ) = "11010" OR CONTROL(7 DOWNTO 2 ) = "110110" ) THEN TMP <= CONV_STD_LOGIC_VECTOR(  ( CONV_INTEGER(INPUT1)+CONV_INTEGER(INPUT2)+CONV_INTEGER(CARRYIN) ) , 9 ) ;
  ELSIF( CONTROL(7 DOWNTO 3 ) = "11110" OR CONTROL(7 DOWNTO 2 ) = "111110" ) THEN TMP <= CONV_STD_LOGIC_VECTOR(  ( CONV_INTEGER(INPUT1)-CONV_INTEGER(INPUT2)-CONV_INTEGER(CARRYIN) ) , 9 ) ;
  END IF ;
  IF ( TMP( 7 DOWNTO 0 ) = "00000000" ) THEN ZERO <= '1' ;
  ELSE ZERO <= '0' ;    
    END IF ; 
      IF( CONTROL(7 DOWNTO 3 ) = "00000" OR CONTROL = "00111000" ) THEN
      TMP( 7 DOWNTO 0 ) <= INPUT1 ; 
      END IF ;
      OUTPUT <= TMP( 7 DOWNTO 0 ) ; 
    CARRYOUT <= TMP(8) ;
      WAIT FOR 1 PS;
END PROCESS ; 
END OPERATION ;

testbench code

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;


ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS
   COMPONENT ALU
  PORT(
      INPUT1 , INPUT2: IN STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; 
      CARRYIN : IN STD_LOGIC ; 
       ZERO,CARRYOUT : OUT STD_LOGIC ; 
       OUTPUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; 
       CONTROL : IN STD_LOGIC_VECTOR(7 DOWNTO 0 )  
        ) ; 
END COMPONENT ; 


   signal i1,i2,ctrl,opt : std_logic_vector(7 downto 0 ) := "00000000" ;
   signal cin,cout,zero : std_logic := '0';


BEGIN


   uut: alu PORT MAP ( i1,i2,cin,zero,cout,opt,ctrl ) ;


  stim_proc: process
   begin        

        i1 <= "10000000" ; 
        i2 <= "10000000" ; 
        ctrl <= "11011010" ; 
        cin <= '0' ; 
        wait for 5 ps;
        ctrl <= "00111000" ; 
        wait for 5 ps ; 
        wait;
  end process;

END;
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2 回答 2

0

不幸的是，这段代码并没有达到您的预期：

CONTROL = "111-11--"

它实际上比较了 CONTROL 以查看它是否将第 4、第 6 和第 7 位设置为-，而不是将它们用作“无关”匹配！令人难以置信，但这就是它多年来被指定工作的方式:(

你想要的是

 std_match(CONTROL, "111-11--")

这将像您期望的那样进行无关紧要的比较。

于 2013-04-19T11:50:30.583 回答
0

问题在于CONTROL = "111-11--"形式的语句以及 'U'|'X'|'W'|'Z'|'-' 在您使用的库函数中的处理方式。

  1. CONTROL = "111-11--" 从 std_logic_unsigned 调用 '=' 函数（比较两个 std_logic_vectors）...
  2. 这从 std_logic_arith 调用 '=' 函数（比较两个无符号值）...
  3. 这从 std_logic_arith 调用 CONV_UNSIGNED ...
  4. 这从 std_logic_arith 调用 MAKE_BINARY ...
  5. 最后，这个函数检查一个位是否设置为'U'|'X'|'W'|'Z'|'-'。如果是这样，它会给出你看到的警告

--> 长答案的短消息：避免使用'U'|'X'|'W'|'Z'|'-'。改为使用“0”和“1”位的显式比较

于 2013-04-19T11:37:07.773 回答