Find centralized, trusted content and collaborate around the technologies you use most.
Teams
Q&A for work
Connect and share knowledge within a single location that is structured and easy to search.
我已经定义
reg bricks[0:3][0:7]
在 Verilog 模块中。如何将此二维数组分配为
{{1,1,1,0,1,1,1},{1,1,1,0,1,1,1},{1,1,1,0,1,1,1},{1,1,1,0,1,1,1}}.
请帮忙
reg bricks [0:3][0:7]; //creates an unpacked array // It means you can access individual bits bricks[1][0] = 0 ; // Assigns 0 to the bit referenced by 1 and 0 bricks [2] = 0 ; // Illegal Syntax bricks [1][0:3] = 0 ; //Illegal Syntax
系统verilog提供了更多的灵活性