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i am pretty a new vhdl user and i am trying to solve a problem,which is difficult for me nowadays . I have two std_logic_vectors.First one has 5 bits,which must have (11111).Second one has 2040 bits,which is arbitral and i must divide up 2040 bits to 24 outputs that means each output must have 85 bits .First i must determine by using a small vector(5bits) the place of successive 5 bits(11111) in a std_logic_vector,which has 2040 bits.After determing if there are (11111) in a 2040bits vector ,the output should be '1' which is responsible 85 bits where there is (11111) .

to summarize

for example i have 24 outputs each control 85 bits of std_logic-vector(2040bits) if there is a 11111 in first 85 bits then output1 should be '1'
if there is a 11111 in 86 to 170 bits then output2 should be '1'
if there is a 11111 in 172 to 255 bits then output3 should be '1' so on...

(11111) is the minimum value .it can be bigger to make an output logic '1' Does someone have any idea about it??... and ((if 2040bits are massive then i can reduce the number of bits))

Thanks

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1 回答 1

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我怀疑您的意思是在第二个向量中搜索第一个向量，但是如果您知道它们都将是 '1'，那么 and_reduce 宏就可以很好地工作。否则用比较替换它。

一般原则是将其分成两个循环，外部用于每个输出结果，内部用于每个可能的 5 位组。该过程可以串行或并行完成，如下所示。

如果 81 to 86 = "11111" 将没有模式匹配，那么您描述问题的方式。如果应该返回 1，则需要稍微更改数组边界。

type slvArray is array (natural range <>) of standard_logic_vector;
subtype outputRange is natural range 0 to 23;
subtype partitionRange is natural range 0 to 84;

proc:process(clock)
    variable andResult : slvArray(outputRange)(partitionRange);
begin
    if rising_edge(clock) then
        for olc in outputRange loop
            for ilc in partitonRange'low to partitionRange'high-4 loop
               andResult(olc)(ilc) <= and_reduce(slv2(olc*partitionRange'length + ilc to olc*partitionRange'length+ ilc + 4);
            end loop;
            output(olc) <= or_reduce(andResult);
        end loop;
    end if;
end process;
于 2013-04-10T20:44:16.297 回答