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我正在开发一个 vhdl 模块。

我想总结 6 个时钟周期的输入值，然后根据是否达到阈值设置输出高或低。

我遇到的问题是，在最后一个时钟周期，总和值没有添加最终输入值。我需要在时钟的上升沿输出高电平。

这是代码：

architecture Behavioral of inputCounter is

signal totalBitWidth     : integer := 6;

-- This signal is specified by the user to determine the majority value
-- for the output.
signal majorityValue     : integer := 4;
signal Sum : integer := 0;

process(clk, input)
    variable clkCount     : integer := 0;
begin
    if input = '1' then
        Sum <= Sum + 1;
    else
        Sum <= Sum + 0;
    end if;

    clkCount := clkCount + 1;

    if clkCount >= (totalBitWidth) then
    -- Determine if the majoritySum variable has met the
    -- threshold for a 1 value
    if Sum >= majorityValue then
    output <= '1';
    else
    output <= '0';
    end if;

    if Sum = totalBitWidth Or Sum = 0 then
    countError <= '0';
    else
    countError <= '1';
    end if;

    -- Reset the clock counter, sum value and majority vector
    clkCount := 0;
    Sum <= 0;

    -- Set the bit counter high to alert other midules that a new bit
    -- has been received
    bitReady <= '1';
end process;
end behavioral;

如果您需要更多信息，请告诉我。谢谢您的帮助。

更新：我在搞乱总和整数，并将其更改为过程中的变量，而不是体系结构中的整体信号。这似乎奏效了。但由于我使用的是 ISim 和 ISE Project navigator，我无法从流程中跟踪变量。

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2 回答 2

1

解决方案是将我的信号更改为过程中的变量。

这是我的代码：

    architecture Behavioral of inputCounter is

signal totalBitWidth     : integer := 6;

signal majorityValue     : integer := 4;
-- This signal is to trace the variable sum
signal SumS              : integer := 0;



begin

-- Process for recognizing a single input value from a 6 clock cycle
-- wide input signal
majority_proc: process(clk, input)
    variable clkCount     : integer := 0;
    variable Sum  : integer := 0;

    begin

        if rising_edge(clk) And enable = '1' then
            -- Reset bitReady after one clock cycle
            bitReady <= '0';

            -- Check the input value and add it to the Sum variable
            if input = '1' then
                Sum := Sum + 1;
            else
                Sum := Sum + 0;
            end if;

            -- Increment the clock counter variable
            clkCount := clkCount + 1;

            -- Check if the clock count has reached the specified number of cycles
            if clkCount >= totalBitWidth then
                -- Determine if the Sum variable has met the threshold for
                -- value of 1, set the output accordingly
                if Sum >= majorityValue then
                    output <= '1';
                else
                    output <= '0';
                end if;

                -- This checks if the value for all clock cycles was the same and
                -- sets an error flag if not
                if Sum = totalBitWidth Or Sum = 0 then
                    countError <= '0';
                else
                    countError <= '1';
                end if;

                -- Reset the clock counter and sum value
                clkCount := 0;
                Sum := 0;

                -- Set the bit counter high to alert other midules that a new bit
                -- has been received
                bitReady <= '1';
            end if;
        end if;

        -- Assign the variable Sum to the signal SumS
        SumS <= Sum;
end process;

end Behavioral;
于 2013-03-14T15:26:58.310 回答
1

如果您必须在获得最后一个输入的同一时钟周期结束时更改输出，则需要将累加器寄存器和加法器分开。将累加器寄存器和输出比较逻辑放入您的进程中，并将加法器拉入异步逻辑。缩写示例代码：

process (clk)
  if rising_edge(clk) and enable='1' then
    accumulator <= sum;
    if sum >= majorityValue then
      output <= '1';
    else
      output <= '0';
    end if;
  end if;
end process;

sum <= accumulator + 1 when input='1' else accumulator;
于 2013-03-14T16:01:02.953 回答